A semiconductor vertical light source includes upper and lower mirrors with an active region in between, an inner mode confinement region, and an outer current blocking region that includes a common epitaxial layer including an epitaxially regrown interface between the active region and upper mirror. A conducting channel including acceptors is in the inner mode confinement region. The current blocking region includes a first impurity doped region with donors between the epitaxially regrown interface and active region, and a second impurity doped region with acceptors between the first doped region and lower mirror. The outer current blocking region provides a PNPN current blocking region that includes the upper mirror or a p-type layer, first doped region, second doped region, and lower mirror or an n-type layer. The first and second impurity doped region force current flow into the conducting channel during normal operation of the light source.

A vertical cavity light-emitting element comprises a substrate, a first multilayer reflector formed on the substrate, a semiconductor structure layer formed on the first multilayer reflector and including a light emitting layer, a second multilayer reflector formed on the semiconductor structure layer and constituting a resonator together with the first multilayer reflector, and a light guide layer configured to form a light guide structure including a center region extending in a direction perpendicular to the upper surface of said substrate between the first and second multilayer reflectors and including a light emission center of the light-emitting layer and a peripheral region provided around the center region and having a smaller optical distance between the first and second multilayer reflectors than that in the center region. The second multilayer reflector has a flatness property over the center region and the peripheral region.

A semiconductor vertical light source includes upper and lower mirrors with an active region in between, an inner mode confinement region, and an outer current blocking region that includes a common epitaxial layer including an epitaxially regrown interface between the active region and upper mirror. A conducting channel including acceptors is in the inner mode confinement region. The current blocking region includes a first impurity doped region with donors between the epitaxially regrown interface and active region, and a second impurity doped region with acceptors between the first doped region and lower mirror. The outer current blocking region provides a PNPN current blocking region that includes the upper mirror or a p-type layer, first doped region, second doped region, and lower mirror or an n-type layer. The first and second impurity doped region force current flow into the conducting channel during normal operation of the light source.

A semiconductor vertical resonant cavity light source includes an upper and lower mirror that define a vertical resonant cavity. An active region is within the cavity for light generation between the upper and lower mirror. At least one cavity spacer region is between the active region and the upper mirror or lower mirror. The cavity includes an inner mode confinement region and an outer current blocking region. An index guide in the inner mode confinement region is between the cavity spacer region and the upper or lower mirror. The index guide and outer current blocking region each include a lower and upper epitaxial material layer thereon with an epitaxial interface region in between. At least a top surface of the lower material layer includes aluminum in the interface region throughout a full area of an active part of the vertical light source.

Optical devices and methods of manufacturing and operating such optical devices. In an embodiment, an optical device includes a substrate, a multi-layer structure having a first surface in contact with a first surface of the substrate, a first mirror disposed over a second surface of the multi-layer structure, a second mirror disposed over a second surface of the substrate, an intermediate mirror within the multi-layer structure, and an optical gain structure within the multi-layer structure. The device may include a first optically resonant cavity within the multi-layer structure, bounded by the first mirror and the intermediate mirror, where the first optically resonant cavity includes the optical gain structure. The device may further include a second optically resonant cavity, bounded by the first and second mirrors, where the second optically resonant cavity includes the first optically resonant cavity, the second optically reflective layer, and the substrate.

A vertical cavity surface emitting laser (VCSEL) array may comprise a first subset of VCSELs of a plurality of VCSELs, and a second subset of VCSELs of the plurality of VCSELs. One or more first beams to be emitted by the first subset of VCSELs, when the VCSEL array is powered, and one or more second beams to be emitted by the second subset of VCSELs, when the VCSEL array is powered, may have different patterns of areas of energy intensity. The different patterns of areas of energy intensity may include respective areas of high energy intensity and respective areas of low energy intensity.

A semiconductor vertical light source includes upper and lower minors with an active region in between, an inner mode confinement region, and an outer current blocking region that includes a common epitaxial layer including an epitaxially regrown interface between the active region and upper minor. A conducting channel including acceptors is in the inner mode confinement region. The current blocking region includes a first impurity doped region with donors between the epitaxially regrown interface and active region, and a second impurity doped region with acceptors between the first doped region and lower minor. The outer current blocking region provides a PNPN current blocking region that includes the upper minor or a p-type layer, first doped region, second doped region, and lower minor or an n-type layer. The first and second impurity doped region force current flow into the conducting channel during normal operation of the light source.

A laser chip including a plurality of stripes is disclosed, where a laser stripe can be grown with an initial optical gain profile, and its optical gain profile can be shifted by using an intermixing process. In this manner, multiple laser stripes can be formed on the same laser chip from the same epitaxial wafer, where at least one laser stripe can have an optical gain profile shifted relative to another laser stripe. For example, each laser stripe can have a shifted optical gain profile relative to its neighboring laser stripe, thereby each laser stripe can emit light with a different range of wavelengths. The laser chip can emit light across a wide range of wavelengths. Examples of the disclosure further includes different regions of a given laser stripe having different intermixing amounts.

The present invention relates to a vertical cavity surface emitting laser (VCSEL) and a manufacturing method thereof, and more specifically, to a high-efficiency oxidized vertical cavity surface emitting laser for emitting laser light having a peak wavelength of 860 nm, and a manufacturing method thereof. The vertical cavity surface emitting laser according to the present invention includes a current diffusion layer having a high doping region at least in a portion between an upper electrode and a lower distributed Bragg reflector.

A non-planarized VCSEL can include: a blocking region over or under an active region, the blocking region having a first thickness; one or more conductive channel cores in the blocking region, the one or more conductive channel cores having a second thickness that is larger than the first thickness, wherein the blocking region is defined by having an implant and the one or more conductive channel cores are devoid of the implant, wherein the blocking region is lateral the one or more conductive channel cores, the blocking region and one or more conductive channel cores being an isolation region; and a non-planarized semiconductor region of one or more non-planarized semiconductor layers over the isolation region. The VCSEL can include a planarized bottom mirror region below the active region and a non-planarized top mirror region above the isolation region, or a non-planarized bottom mirror region below the active region.