A radio frequency integrated circuit (RFIC) device includes: a first RF input/output (I/O) terminal; a second RF I/O terminal, where the first and the second RF I/O terminals are configured to transmit or receive an RF signal; a capacitor coupled between the first and the second RF I/O terminals; a first coil coupled between the first and the second RF I/O terminals, where the first coil is configured to provide ESD protection to the capacitor during a first ESD event; and a fast transient ESD protection circuit coupled between the first and the second RF I/O terminals, where the fast transient ESD protection circuit is configured to provide ESD protection to the capacitor during a second ESD event different from the first ESD event, where a first rise time of the first ESD event is longer than a second rise time of the second ESD event.

High voltage clamps with transient activation and activation release control are provided herein. In certain configurations, an integrated circuit (IC) includes a clamp electrically connected between a first node and a second node and having a control input. The IC further includes a first resistor-capacitor (RC) circuit that activates a detection signal in response to detecting a transient overstress event between the first node and the second node, an active feedback circuit that provides feedback from the first node to the control input of the clamp in response to activation of the detection signal, a second RC circuit that activates a shutdown signal after detecting passage of the transient overstress event based on low pass filtering a voltage difference between the first node and the second node, and a clamp shutdown circuit that turns off the clamp via the control input in response to activation of the shutdown signal.

An electrostatic discharge protection circuit for an integrated circuit and a method for electrostatic discharge protection thereof are disclosed. The integrated circuit includes a power source, a ground, a signal input, and a signal output. The integrated circuit further comprises one or more essentially identically configured electrostatic discharge protection circuits, configured to provide electrostatic discharge protection between any two of the power source, the ground, the signal input, and the signal output. A method of providing electrostatic discharge protection includes providing one or more essentially identically configured electrostatic discharge protection circuits coupled between and providing electrostatic discharge protection for any two of the power source, the ground, the signal input, and the signal output. The disclosed integrated circuit and method provide advantages of simplifying the integrated circuit design and reducing design time.

An electrostatic discharge (ESD) protection device includes a first clamping circuit, a second clamping circuit, and a diode circuit. The first clamping circuit is coupled between a first power rail and a second power rail. The second clamping circuit is coupled between a third power rail and the second power rail. The diode circuit is configured to steer an ESD current from an input/output pad to at least one of the first clamping circuit or the third power rail. The first power rail receives a first voltage, the second power rail receives a second voltage, the third power rail receives a third voltage, the third voltage is higher than the first voltage, and the first voltage is higher than the second voltage.

A display panel and a display apparatus are disclosed. The display panel comprises: a plurality of signal lines extending in a first direction; at least one first reference voltage bus which extends in a second direction intersecting the first direction; and a plurality of electrostatic discharge units divided into a plurality of electrostatic discharge unit groups, wherein the plurality of electrostatic discharge unit groups are arranged in the second direction and each of the plurality of electrostatic discharge unit groups comprises at least two electrostatic discharge units arranged in the first direction, wherein at least one of the plurality of signal lines is electrically connected to the first reference voltage bus through at least one of the plurality of electrostatic discharge units.

An electrostatic discharge (ESD) protection circuit includes an ESD detector connected between a pad and a first power source and configured to generate a detection signal when ESD is detected at the pad, a switch transistor including a gate controlled by the detection signal and a source and a drain connected between the pad and the memory, and a leakage current prevention circuit including a first transistor including a first gate connected to a second power source and a source and a drain connected between the pad and a first node, and a second transistor including a second gate connected to the pad and a source and a drain connected between the first node and the second power source. The first node is connected to or in electrical communication with a bulk node of the switch transistor.

An electronic device includes a first group III nitride transistor and an electrostatic discharge (ESD) protection circuit. an electronic device may include a first group III nitride transistor and an ESD protection circuit. The ESD protection circuit may include a first transistor, a second transistor, and a third transistor. The first transistor may have a source and a gate connected to each other and electrically connected to a gate of the first group III nitride transistor. The second transistor may have a source and a gate connected to each other and electrically connected to a source of the first group III nitride transistor. The third transistor may have a drain electrically connected to the gate of the first group III nitride transistor, a gate electrically connected to a drain of the first transistor and to a drain of the second transistor, and a source electrically connected to the source of the first group III nitride transistor.

The protection circuit includes a detection circuit and a discharge circuit. The detection circuit is coupled to first and second power bonding pads and detects whether an ESD event or an EOS event occurs at the first power bonding pad. The detection circuit controls a detection voltage on a detection node according to a detection result. The first and second power bonding pads belong to different power domains. The discharge circuit is coupled to the detection node and the first power pad. In response to the ESD event occurring at the first power bonding pad, the discharge circuit provides a discharge path between the first power bonding pad and a ground terminal according to the detection voltage. In response to the EOS event occurring at the first power bonding pad, the detection circuit activates a second discharge path between the first power bonding pad and the ground terminal.

In accordance with an embodiment, a semiconductor device includes: an n-doped region disposed over an insulating layer; a p-doped region disposed over the insulating layer adjacent to the n-doped region, where an interface between the n-doped region and the p-doped region form a first diode junction; a plurality of segmented p-type anode regions disposed over the insulating layer, each of the plurality of segmented p-type anode regions being surrounded by the n-doped region, where a doping concentration of the plurality of segmented p-type anode regions is greater than a doping concentration of the p-doped region; and a plurality of segmented n-type cathode regions disposed over the insulating layer. Each of the plurality of segmented n-type cathode regions are surrounded by the p-doped region, where a doping concentration of the plurality of segmented n-type cathode regions is greater than a doping concentration of the n-doped region.

The present disclosure provides an electrostatic discharge (ESD) protection circuit for a chip, including: a monitoring unit, configured to generate a trigger signal when there is an ESD pulse on a power supply pad; a discharge transistor, located between the power supply pad and a ground pad, and configured to be turned on under a control of the trigger signal, so as to discharge an electrostatic charge to the ground pad; and a first controllable voltage division unit, connected to the discharge transistor, and configured to switch an operating mode under a control of a control signal. The operating mode includes a voltage division mode. When operating in the voltage division mode, the controllable voltage division unit is configured to carry a part of a voltage applied by the electrostatic charge to the discharge transistor.