The disclosure generally relates to a conductive layer having one or more protrusions configured to attract an electrostatic discharge (“ESD”) arc. The device may be any device, such as a smartphone, tablet, earbuds, etc. The device may include a microphone and, therefore, may include a microphone opening. The conductive layer may include a conductive opening axially aligned with the microphone opening and one or more protrusions extending radially inwards towards the center of the conductive opening.

Systems and methods for RF hazard protection are provided. In one embodiment, a RF protection coupler comprises: a first port to couple to an output of an RF source circuit; a second port to couple to an external RF load; a source side and load side RF switches, wherein the source side RF switch and the load side RF switch are each switch between a first and second states in response to a detected matting. In the first state the source and load side RF switches establish an electrical path between the first and second ports. In the second state: the source side RF switch couples the first port to an impedance load that is impedance matched to the output of the RF source circuit; the load side RF switch couples the second port to an electrical ground; and a gap between the switches electrically isolates the ports.

An integrated circuit includes a signal pad, receiving an input signal during a normal mode, and receive an ESD signal during an ESD mode; an internal circuit, processing the input signal during the normal mode; a variable impedance circuit, comprising a first end coupled to the signal pad, a second end coupled to the internal circuit, wherein the variable impedance circuit provides a low or high impedance path between the signal pad and the internal circuit during the normal or ESD mode; and a switch circuit, comprising a first end coupled to a control end of the variable impedance circuit, a second end coupled to a reference voltage terminal, and a control end receiving a node voltage, wherein the switch circuit switches the control end of the variable impedance circuit to have a first specific voltage or be electrically floating during the normal or ESD mode.

The present disclosure relates to the technical field of semiconductors, and provides an electro-static discharge (ESD) protection structure and a chip. The ESD protection structure includes: a semiconductor substrate, a first P-type well, a first N-type well, a first N-type doped portion, a first P-type doped portion, a second N-type doped portion, a second P-type doped portion, a third doped well, a third P-type doped portion and a third N-type doped portion, wherein the first P-type well, the first N-type well and the third doped well are located in the semiconductor substrate; the first N-type doped portion and the first P-type doped portion are located in the first N-type well and spaced apart; the second N-type doped portion and the second P-type doped portion are located in the first P-type well and spaced apart.

Aspects of this disclosure relate to detecting and recording information associated with electrical overstress (EOS) events, such as electrostatic discharge (ESD) events. For example, in one embodiment, an apparatus includes an electrical overstress protection device, a detection circuit configured to detect an occurrence of the EOS event, and a memory configured to store information indicative of the EOS event.

This disclosure relates to a semiconductor device including a device with high clamping voltage (HVC device), and an OTS device. Such a semiconductor device provides very advantageous ESD protection. The semiconductor device can be realized in two ways: an OTS device and a device with high clamping voltage can be realized as discrete, independent devices that are combined in one semiconductor package, or an OTS device can be integrated into interconnect layers of a device with high clamping voltage by integration.

An electrostatic discharge (ESD), protection device is provided. In accordance with the present disclosure, an ESD protection device is provided that includes a series connection of a first unit having strong snapback and low series capacitance and a second high-voltage unit that displays a relatively high holding/trigger voltage to ensure latch up and improper triggering of the ESD protection device while at the same time providing high-voltage operation with low capacitive loading.

An integrated circuit is provided with a protected circuit wherein a first FinFET operably coupled to a signal node is protected against electrostatic discharge voltage damage by a standard cell electrostatic discharge protection circuit which is connected between first and second voltage supplies and which includes a first FinFET diode connected between the signal node and the first voltage supply, and a second FinFET diode connected between the signal node and the second voltage supply, where the first and second FinFET diodes are each formed with a FinFET device comprising (1) a body well region forming a first diode terminal connected to one of the first or second voltage supplies, and (2) a shorted gate, source, and drain regions forming a second diode terminal connected to the signal node.

Provided is an electrostatic discharge protection circuit, including a first resistor, a first transistor, a second resistor, and a second transistor. The first resistor has a first end coupled to a first power rail. The first transistor has a first end coupled to the first power rail, and a control end of the first transistor is coupled to a second end of the first resistor. The second resistor is coupled between a second end of the first transistor and a second power rail. The second transistor has a first end coupled to the first power rail, a control end of the second transistor is coupled to the second end of the first transistor, and a second end of the second transistor is coupled to the second power rail.

An electronic device includes a first group III nitride transistor and an electrostatic discharge (ESD) protection circuit. The ESD protection circuit includes a diode and a second transistor. The diode has an anode electrically connected to a gate of the first group III nitride transistor. The second transistor has a drain electrically connected to the gate of the first group III nitride transistor, a gate electrically connected to a cathode of the diode and a source electrically connected to a source of the first group III nitride transistor.