A power converter includes an unfolder connected to a three-phase source and has an output connection with three output terminals. A three-input converter connected to the unfolder produces a quasi-sinusoidal output voltage across converter output terminals. Switches of the converter selectively connect each of the three output terminals across the converter output terminals. A pulse-width modulation controller controls a first duty ratio and a second duty ratio for the converter based on a phase angle of the source and a modulation index generated from an error signal related to a control variable. The duty ratios are time varying at a rate related to a fundamental frequency of the source. The modulation index relates to output voltage of the converter, peak voltage or current of the source and/or peak current at the output terminals.

Power converters with power factor correction circuits and controllers thereof that are configured to generate frequency-adjustable first and second pulsed signals having respective and complementary phases separated by an adjustable deadtime. For example, a power converter may be configured to receive an alternating current (AC) input signal and output a direct current (DC) output signal. The power converter may include a transformer and a power factor correction circuit. The power factor correction circuit may include: a first switching transistor and a second switching transistor in series with the first switching transistor; and a controller configured to generate first and second pulsed signals having respective and complementary phases and separated by an adjustable deadtime and apply the generated first and second pulsed signals to the first and second transistors, respectively. A primary side of the transformer may be coupled to a node between the first and second switching transistors.

Power factor correction circuits and controllers thereof that are configured to generate frequency-adjustable first and second pulsed signals having respective and complementary phases separated by an adjustable deadtime. For example, a controller for a power factor correction circuit may include a comparator, a frequency controller, and a deadtime controller. The controller may be configured to: receive an input signal comprising a measured output voltage of the power factor correction circuit; compare, via the comparator, the measured output voltage with a set point, resulting in a difference between the measured output voltage and the set point; feed the difference into the frequency controller and adjust a frequency of the first and second pulsed signals based on an output of the frequency controller; and provide the difference to the deadtime controller and adjust the deadtime of the first and second pulsed signals based on an output of the deadtime controller.

A power supply apparatus, comprising at least one circuit board having thereon at least a first single phase power factor controlled (PFC) circuit, and a second PFC corrected circuit, the first single phase PFC circuit and the second PFC corrected circuit each having at least one PFC device in communication with at least one inverter, at least one resonant (LC) circuit positioned on the at least one circuit board and in electrical communication with at least one of the first single phase PFC circuit and the second PFC corrected circuit, at least one transformer in communication with at least one of the first single phase PFC circuit and the second PFC corrected circuit via the at least one LC resonant circuit, the at least one transformer configured to generate at least one transformer output signal, and at least one capacitor in communication with the at least one transformer and configured to output at least one magnetron input signal in response to the at least one transformer output signal, and at least one power supply generating at least one three phase input voltage, the at least one circuit board in communication with the at least one power supply.

Methods and systems include identifying an abnormal condition in a PFC circuit comprising an input configured to be coupled to a 3-phase power source and to receive input 3-phase power from the 3-phase power source, a bus having a plurality of bus lines, each bus line configured to be coupled to the input and to carry one phase of the input 3-phase power, a PFC leg including a contactor configured to selectively couple a capacitor bank included in the PFC leg to the bus. In response to identifying the abnormal condition, the contactor is controlled to decouple the capacitor bank from the bus, and after a reset button has been activated, the contactor is recoupled to the capacitor bank to resume operating the PFC leg to provide power factor correction to the input 3-phase power.

The present disclosure provides a three-phase AC/DC converter aiming for low input current harmonic. The converter includes an input stage for receiving a three-phase AC input voltage, an output stage for at least one load, and one or more switching conversion stages, each stage including a plurality of half bridge modules. The switches in each module operate with a substantially fixed 50% duty cycle and are connected in a specific pattern to couple a DC-link and a neutral node of the input voltage. The AC/DC converter further includes one or more controllers adapted to vary the switching frequency of the switches in the switching conversion stages based on at least one of load voltage, load current, input voltage, and DC-link voltage. The converter can also include one or more decoupling stages, such as, inductive components adapted to decouple the output stage from the switching conversion stages.

A matrix power conversion device including a plurality of three-phase switching modules and a controller is provided. Each three-phase switching module includes a plurality of bidirectional switches connected to the input phase voltages of the three-phase input power respectively and outputs a corresponding output phase voltage of the three-phase output power. The controller determines a maximum voltage, an intermediate voltage and a minimum voltage among all the input phase voltages to acquire a waveform of a control carrier wave in a switching cycle. The controller acquires output expected values corresponding to all output phase voltages and compares them with the waveform of the control carrier wave for acquiring a turning-on time of each of the plurality of bidirectional switches. Accordingly, the controller controls the matrix power conversion device to switch the three-phase input power so as to change the three-phase output power for driving the motor.

A method and apparatus are described for compensating input voltage ripples of an interleaved boost converter using cycle times. In an embodiment, a phase compensator receives a first duty cycle measurement of a first converter and a second duty cycle measurement of a second converter, compares the first duty cycle to the second duty cycle and generates a phase compensation in response thereto. A phase combiner combines a phase adjustment output and the phase compensation and produces a phase control output, and a cycle controller is coupled to the first and the second converters to generate a first drive signal to control switching of the first converter and to generate a second drive signal to control switching of the second converter, wherein a time of the second drive signal is adjusted using the phase control output.

A circuit arrangement configured to execute DC link processing with simultaneous reduction of the harmonic components in the input current, i.e., for usability or applicability in different power supply networks, particularly both in single-phase and three-phase networks with the same circuit topology or in the event of the failure of a phase.

A switched capacitor bank assembly including a first capacitor, a first switch selectively connected between the first capacitor and a first phase line, and a first voltage sensor integrated within a housing of the first switch and configured to sense a voltage of the first phase line. The assembly further includes a controller including an electronic processor, the controller operably coupled to the first voltage sensor and the first switch. The first capacitor, the first switch, the first voltage sensor, and the controller are physically supported by a frame of the switched capacitor bank assembly.