An apparatus includes a PWM ramp generator coupled between a switching node of a power converter and a first input of a comparator, the PWM ramp generator comprising a first resistor and a first capacitor connected in series between the switching node and the first input of the comparator, and a second resistor and a second capacitor connected in parallel between the first input of the comparator and a feedback node, and a PFM control circuit comprising an error amplifier and a current zero crossing detection comparator, wherein the error amplifier is coupled between a second input of the comparator and a reference node, and the PFM control circuit is configured to generate gate drive signal for the power converter when the power converter is configured to operate in a PFM mode.

An isolation circuit that isolates a driver circuit that is biased at a first common mode voltage from a detection circuit that is biased at a second common mode voltage using isolation capacitors. The detection circuit includes a transimpedance amplifier having improved susceptibility to transient common-mode input signals and improved insensitivity to parasitic capacitance on the isolation capacitor terminals. Included within the transimpedance amplifier are circuits for mirroring current to convert the input current from the isolation capacitors into a voltage value and to amplify that voltage value. The transimpedance amplifier outputs a differential voltage value that is held by a latch circuit so that a comparator in the detection circuit can process the differential voltage value and output a differential signal with fully restored logic levels.

An isolation circuit that isolates a driver circuit that is biased at a first common mode voltage from a detection circuit that is biased at a second common mode voltage using isolation capacitors. The detection circuit includes a transimpedance amplifier having improved susceptibility to transient common-mode input signals and improved insensitivity to parasitic capacitance on the isolation capacitor terminals. Included within the transimpedance amplifier are circuits for mirroring current to convert the input current from the isolation capacitors into a voltage value and to amplify that voltage value. The transimpedance amplifier outputs a differential voltage value that is held by a latch circuit so that a comparator in the detection circuit can process the differential voltage value and output a differential signal with fully restored logic levels.

A voltage divider circuit arrangement includes a resistive divider circuit portion constructed from first and second resistors (R1, R2) The first and second resistors are connected in series and are arranged to provide a refresh voltage (Vrefresh) at a refresh node between them. A capacitive divider circuit portion is constructed from first and second capacitors (C1, C2). The first and second capacitors are connected in series and are arranged to provide an output voltage (Vout) at an output node. A switching circuit portion is arranged intermittently to switch the voltage divider circuit arrangement between a first mode wherein the resistive divider is enabled and the output node is connected to the refresh node, and a second mode wherein the resistive divider is disabled and the output node is not connected to the refresh node.

A voltage divider circuit arrangement includes a resistive divider circuit portion constructed from first and second resistors (R1, R2) The first and second resistors are connected in series and are arranged to provide a refresh voltage (Vrefresh) at a refresh node between them. A capacitive divider circuit portion is constructed from first and second capacitors (C1, C2). The first and second capacitors are connected in series and are arranged to provide an output voltage (Vout) at an output node. A switching circuit portion is arranged intermittently to switch the voltage divider circuit arrangement between a first mode wherein the resistive divider is enabled and the output node is connected to the refresh node, and a second mode wherein the resistive divider is disabled and the output node is not connected to the refresh node.

Embodiments described herein provides a battery charging circuit that boosts an input current and feeds the boosted input current to a battery for fast charging. Specifically, the battery charging circuit includes a low dropout regulator (LDO) for providing a voltage, a switch mode charger, coupled between the LDO and a battery, and a capacitor divider, coupled between the LDO and the battery, in parallel to the switch mode charger, for dividing the voltage outputted from the LDO by a factor.

A power control circuit comprising a power supply and a load, the load being synthesized from an impedance synthesizer comprising two-terminal impedance elements connected in series and grouped in impedance modules. The impedance elements in each impedance module are of equal value, while those between the modules bear ratios uniquely defined according to the numbers of impedance elements in the impedance modules. A number of switches associated with said impedance elements short out a selected number of the impedance elements under the control of a first analog signal which may be preprocessed by an analytic function. The analog signal is converted to digital signals by an analog-to-digital converter, then level shifted to control the switches associated with the impedance elements, whereby the amount of power delivered to the load is controllable by the first analog signal. Pulse-width-modulation is deployed to further control the power by a second analog signal, with additional benefit of overload protection.

An adjustable three output DC voltage supply circuit includes positive and negative DC voltage buses that connect to a DC power source; a first voltage divider connected between the positive and negative DC voltage buses and including a shunt regulator that is connected to the positive DC voltage bus and that provides an intermediate voltage supply; a second voltage divider connected between the positive or the negative DC voltage bus and the intermediate voltage supply and including an output that is connected to a reference input of the shunt regulator; and a short circuit protection component connected in series to a low voltage side of the shunt regulator and configured to limit the current through the shunt regulator in the case of a short circuit to the intermediate voltage supply.

An adjustable three output DC voltage supply circuit includes positive and negative DC voltage buses that connect to a DC power source; a first voltage divider connected between the positive and negative DC voltage buses and including a shunt regulator that is connected to the positive DC voltage bus and that provides an intermediate voltage supply; a second voltage divider connected between the positive or the negative DC voltage bus and the intermediate voltage supply and including an output that is connected to a reference input of the shunt regulator; and a short circuit protection component connected in series to a low voltage side of the shunt regulator and configured to limit the current through the shunt regulator in the case of a short circuit to the intermediate voltage supply.

A power supply circuit for providing a positive, intermediate, and negative voltage supply includes positive and negative DC voltage buses that connect to a power source; a first voltage divider that is connected between the positive and the negative DC voltage buses, that includes a first transistor connected to the negative DC voltage bus, and that provides the intermediate voltage supply; a second voltage divider that is connected between the positive and the negative DC voltage buses and that is connected to the first transistor; and a short circuit protection module that includes a second transistor connected between outputs of the first and second voltage dividers and connected to the first transistor and that includes a current limiting element connected to the first transistor and configured to limit power dissipated by the first transistor in the case of a short circuit to the intermediate voltage supply.