An oscillator includes first and second capacitors, an inverter, a voltage shifting circuit, and a hysteresis buffer. The first and second capacitors have first terminals adapted to be coupled to respective first and second nodes, and second terminals coupled to ground. The inverter has an input coupled to the first node, and an output coupled to the second node. The voltage shifting circuit is coupled to the first and second nodes and has an input for receiving a tuning signal. The voltage shifting circuit changes an average voltage at the first node according to the tuning signal when an oscillation occurs in response to a crystal being coupled between the first and second nodes. The hysteresis buffer has an input coupled to one of first node and the second node, and an output for providing a clock signal having a duty cycle responsive to the tuning signal.

A variable capacitance circuit includes a capacitor array having a first capacitor in which a plurality of MIM capacitors are coupled in parallel and a second capacitor in which a plurality of MIM capacitors are coupled in series, and a switch array having a first switch and a second switch. A shape pattern of at least one of a first electrode of the first capacitor, a first ground shield, a second electrode of the second capacitor, and a second ground shield is set so that a first capacitance difference per 1 LSB between first capacitance values of the first capacitor when the first switch is turned on and off and a second capacitance difference per 1 LSB between second capacitance values of the second capacitor when the second switch is turned on and off are close to each other.

A variable capacitance circuit includes a capacitor array having a first capacitor in which a plurality of MIM capacitors are coupled in parallel and a second capacitor in which a plurality of MIM capacitors are coupled in series, and a switch array having a first switch and a second switch. A shape pattern of at least one of a first electrode of the first capacitor, a first ground shield, a second electrode of the second capacitor, and a second ground shield is set so that a first capacitance difference per 1 LSB between first capacitance values of the first capacitor when the first switch is turned on and off and a second capacitance difference per 1 LSB between second capacitance values of the second capacitor when the second switch is turned on and off are close to each other.

A method of operating an oscillator circuit comprising a resonator is provided. The method comprises maintaining a resonance of the resonator by a) connecting the resonator to an input voltage (V.sub.buf) for a first pulse period to charge the resonator only partially towards the input voltage (V.sub.buf); b) connecting the resonator to a second, lower, voltage for a second pulse period to discharge the resonator at least partially; and repeating steps a) and b) at a rate corresponding to the resonance of the resonator and with a phase corresponding to the resonance of the resonator, so as to maintain the resonance of the resonator.

A method of operating an oscillator circuit comprising a resonator is provided. The method comprises maintaining a resonance of the resonator by a) connecting the resonator to an input voltage (V.sub.buf) for a first pulse period to charge the resonator only partially towards the input voltage (V.sub.buf); b) connecting the resonator to a second, lower, voltage for a second pulse period to discharge the resonator at least partially; and repeating steps a) and b) at a rate corresponding to the resonance of the resonator and with a phase corresponding to the resonance of the resonator, so as to maintain the resonance of the resonator.

A method for providing a reference clock signal, comprising: generating, by an oscillator, a first clock signal having a first frequency, the first clock signal being coupled to a frequency synthesizer; generating, by the frequency synthesizer, a second clock signal based on the first clock signal, the second clock signal having a second frequency different from the first frequency; outputting a reference clock signal to one or more components of an electronic device, the reference clock signal being one of the first clock signal or the second clock signal; identifying one or more spurious frequency components; and monitoring the reference clock signal for a presence of the one or more spurious frequency components, the monitoring comprising: in response to determining the presence of at least one of the one or more spurious frequency components, selecting a different one of the first clock signal or the second clock signal to be the reference clock signal.

A method for providing a reference clock signal, comprising: generating, by an oscillator, a first clock signal having a first frequency, the first clock signal being coupled to a frequency synthesizer; generating, by the frequency synthesizer, a second clock signal based on the first clock signal, the second clock signal having a second frequency different from the first frequency; outputting a reference clock signal to one or more components of an electronic device, the reference clock signal being one of the first clock signal or the second clock signal; identifying one or more spurious frequency components; and monitoring the reference clock signal for a presence of the one or more spurious frequency components, the monitoring comprising: in response to determining the presence of at least one of the one or more spurious frequency components, selecting a different one of the first clock signal or the second clock signal to be the reference clock signal.

A circuit device includes an oscillation circuit configured to generate an oscillation signal, a first pre-driver disposed in a posterior stage of the oscillation circuit, a first output driver disposed in a posterior stage of the first pre-driver, a first regulator configured to supply a first regulated voltage to the first pre-driver, and a second regulator configured to supply a second regulated voltage to the first output driver, wherein the second regulator is shorter in transient response time than the first regulator.

A circuit apparatus includes an oscillation circuit that generates an oscillation signal, a first buffer circuit that outputs a first clock signal based on the oscillation signal, a second buffer circuit that outputs a second clock signal based on the first clock signal, a first terminal electrically couplable to a first node via which the first buffer circuit outputs the first clock signal, and a second terminal electrically coupled to a second node via which the second buffer circuit outputs the second clock signal, and the rise period of the first clock signal is shorter than the rise period of the second clock signal.

A circuit apparatus includes an oscillation circuit that generates an oscillation signal, a first buffer circuit that outputs a first clock signal based on the oscillation signal, a second buffer circuit that outputs a second clock signal based on the first clock signal, a first terminal electrically couplable to a first node via which the first buffer circuit outputs the first clock signal, and a second terminal electrically coupled to a second node via which the second buffer circuit outputs the second clock signal, and the rise period of the first clock signal is shorter than the rise period of the second clock signal.