A mixing stage includes a first modulation stage that receives an input signal from a first common node of the mixing stage, a first local oscillator input that receives a local oscillator signal, and a first modulation signal output adapted to provide a first modulated signal. A second modulation stage of the mixing stage includes a second input that receives a phase inverted representation of the input signal from a second common node of the mixing stage, a second local oscillator input that receives the local oscillator signal, and a second modulation signal output adapted to provide a second modulated signal. A current generation circuit provides a supply current to the first common node and to the second common node. A current control circuit is adapted to superimpose an offset current to the current of at least one node of the first common node and the second common node.

The method determines an input phase differential () between two input signals. A phase detector is provided that has pairs of transistors and a first impedance (R1) connected to a first branch carrying a first signal (Iout_left) and a second impedance (R2) connected to a second branch carrying a second signal (Iout_right). The first signal (Iout_left) in the first branch is set as a first sum of a common mode output signal (Icm) and a differential mode output signal (Idm). The second signal (Iout_right) in the second branch is set as a second sum of the common mode output signal (Icm) minus the differential mode output signal (Idm). A relationship between the first impedance (R1) and the second impedance (R2) is adjusted until a differential mode output voltage (Vdm) of the phase detector is zero. The input phase differential () is determined when the differential mode output voltage (Vdm) is zero.

A mixing stage includes a first modulation stage that receives an input signal from a first common node of the mixing stage, a first local oscillator input that receives a local oscillator signal, and a first modulation signal output adapted to provide a first modulated signal. A second modulation stage of the mixing stage includes a second input that receives a phase inverted representation of the input signal from a second common node of the mixing stage, a second local oscillator input that receives the local oscillator signal, and a second modulation signal output adapted to provide a second modulated signal. A current generation circuit provides a supply current to the first common node and to the second common node. A current control circuit is adapted to superimpose an offset current to the current of at least one node of the first common node and the second common node.

The method determines an input phase differential () between two input signals. A phase detector is provided that has pairs of transistors and a first impedance (R1) connected to a first branch carrying a first signal (Iout_left) and a second impedance (R2) connected to a second branch carrying a second signal (Iout_right). The first signal (Iout_left) in the first branch is set as a first sum of a common mode output signal (Icm) and a differential mode output signal (Idm). The second signal (Iout_right) in the second branch is set as a second sum of the common mode output signal (Icm) minus the differential mode output signal (Idm). A relationship between the first impedance (R1) and the second impedance (R2) is adjusted until a differential mode output voltage (Vdm) of the phase detector is zero. The input phase differential () is determined when the differential mode output voltage (Vdm) is zero.

An electronic device includes a transimpedance amplifier stage having an amplifier end stage of the class AB type and a preamplifier stage coupled between an output of a frequency transposition stage and an input of the amplifier end stage. A self-biased common-mode control stage is configured to bias the preamplifier stage. The preamplifier stage is formed by a differential amplifier with an active load that is biased in response to the self-biased common-mode control stage.

Each unit cell (4a-1 to 4a-N) of the distributed double balanced mixer outputs a signal (R++) obtained by multiplexing the LO signal (LO+) on the positive phase side and the IF signal (IF+) on the positive phase side, a signal (RF) obtained by multiplexing the LO signal (LO) on the negative phase side and the IF signal (IF) on the negative phase side, a signal (RF+) obtained by multiplexing the LO signal (LO) on the negative phase side and the IF signal (IF+) on the positive phase side, and a signal (RF+) obtained by multiplexing LO signal (LO+) on the positive phase side and IF signal (IF) on the negative phase side, to transmission lines (CPW20pp, CPW20nn, CPW20np, CPW20pn), without synthesizing the signals.

An apparatus is disclosed for oscillator leakage calibration. In example aspects, the apparatus includes a mixer circuit and calibration circuitry. The mixer circuit has a first stage including at least one transistor coupled between a mixer input and a mixer output and a second stage including one or more transistors coupled between the at least one transistor and the mixer output. The mixer circuit also has tuning circuitry coupled to the at least one transistor. The calibration circuitry includes at least one resistor coupled between a power distribution node and at least one mixer node, with the at least one mixer node coupled between the at least one transistor and the one or more transistors, and at least one switch coupled between the power distribution node and the at least one mixer node. The calibration circuitry also includes controller circuitry coupled between the mixer node and the tuning circuitry.

A method, an apparatus, and a system product for mixing radio frequency signals are provided. In one aspect, the apparatus is configured to perform switching of switches based on first, second, third, and fourth phased half duty clock signals. The apparatus convolves a differential input signal on a differential input port with the first, second, third, and fourth phased half duty cycle clock signals to concurrently generate a differential in-phase output signal and a differential quadrature-phase output signal on a dual differential output port. The first, second, third, and fourth phased half duty cycle clock signals are of the same frequency and out of phase by a multiple of ninety degrees with respect to each other.