Analog multipliers can perform signal processing with approximate precision asynchronously (clock free) and with low power consumptions, which can be advantageous including in emerging mobile and portable artificial intelligence (AI) and machine learning (ML) applications near or at the edge and or near sensors. Based on low cost, mainstream, and purely digital Complementary-Metal-Oxide-Semiconductor (CMOS) manufacturing process, the present invention discloses embodiments of current-mode analog multipliers that can be utilized in multiply-accumulate (MAC) signal processing in end-application that require low cost, low power consumption, (clock free) and asynchronous operations.

A power detector with a main transconductance stage and a Gilbert switch stage coupled to one another. Current sources are coupled between the main transconductance and the Gilbert switch stages. Each of the current sources is configured to generate a cascoded PMOS trickle current under the control of a DAC to control the effective voltage of the Gilbert switch stage. This mitigates the DC offsets resulting in enhanced sensitivity of the Gilbert switch stage. An increase in the conversion gain of a system using a Gilbert switch stage, for a given LO swing, is therefore obtained for a very small increase in DC power.

A combined mixer and filter circuitry is disclosed. The combined mixer and filter circuitry comprises a mixer comprising a first input, a second input and an output. The combined mixer and filter circuitry further comprises a filter comprising an active inductor and a first capacitor. The active inductor comprises a transistor having a first terminal, a second terminal and a third terminal and a resistor connected between the first terminal of the transistor and a voltage potential. The first capacitor is connected between the third terminal and a signal ground and the second terminal of the transistor is connected to the second input of the mixer.

An apparatus is disclosed for mixing signals with a multi-mode mixer for frequency translation. In example implementations, a multi-mode mixer includes a supply voltage node, a ground node, a first data signal coupler, and a second data signal coupler. The multi-mode mixer also includes a mixer core and a current control switch. The mixer core is coupled between the first data signal coupler and the second data signal coupler. The current control switch is configured to selectively enable or disable flow of a current through the mixer core. The first data signal coupler, the second data signal coupler, the mixer core, and the current control switch are coupled together in series between the supply voltage node and the ground node.

The present invention provides a receiver including a first band group, a second band group and a mixer. The first band group includes at least one LNA, wherein the first band group is configured to select one first LNA to receive a first input signal to generate an amplified first input signal. The second band group includes at least one LNA, wherein the second band group is configured to select one second LNA to receive a second input signal to generate an amplified second input signal. The first band group and the second band group are coupled to a first input terminal and a second input terminal of the mixer, respectively, and the mixer receives one of the amplified first input signal and the amplified second input signal to generate an output signal.

A phase adjustment circuit includes: a local frequency band phase shifter that adjusts a phase of a signal in a local signal frequency band and that outputs the adjusted signal; a frequency-converting mixer that receives the adjusted signal and another signal different from the adjusted signal, and that mixes the adjusted signal with the other signal; and a buffer amplifier that is provided between the local frequency band phase shifter and the frequency-converting mixer, and that is capable of amplifying an input power that is to be input to the frequency-converting mixer so that the input power is up to be in an input power range in which an input-output characteristic of power of the frequency-converting mixer is out of a linear region.

A method for initializing a phase adder circuit including a multiplier circuit with its two inputs receiving signals of frequency f.sub.o, a mixer circuit, an amplifier circuit, a low pass loop filter, and a voltage controlled oscillator (VCO), the method including: during a first phase, determining a reference voltage which when applied to the VCO causes it to produce a signal having a frequency of nf.sub.0; during a second phase, supplying a signal of frequency nf.sub.o to a first input of the mixer and a signal of frequency (nf.sub.o+f) to a second input of the mixer; and determining an adjustment signal which when applied to the amplifier circuit causes the amplifier circuit to output a signal having a DC component equal to the reference voltage; and during a third phase, forming a primary phase locked loop (PLL) circuit including the mixer, the amplifier circuit, the low pass loop filter and the VCO; and applying the adjustment signal to the amplifier circuit.

A circuit includes a first signal swapper including a first terminal coupled to a first current source, a second terminal coupled to a second current source, a third terminal coupled to a first current terminal of a first transistor, and a fourth terminal coupled to a third current terminal of a second transistor. The first signal swapper couples the first and second terminals to the third and fourth terminals responsive to a first control signal. First and second switches couple to a gate of the first transistor. The first switch receives the input oscillation signal and the second switch receives a first reference voltage. Third and fourth switches couple to a gate of the second transistor. The third switch receives the input oscillation signal and the fourth switch receives the first reference voltage. A second signal swapper couples to the first signal swapper and to the first and second transistors.

An integrated amplifier device includes a main amplifier configured to be coupled to an input source. A replica amplifier is coupled to the main amplifier to provide a bias to the main amplifier. A transconductance biasing cell to the main amplifier and the replica amplifier. The transconductance biasing cell is configured to bias both the main amplifier and the replica amplifier. A method of making an integrated amplifier device is also disclosed.

The disclosure relates to technology for an apparatus having a current conveyer comprising a first stage having a first differential input, and a second stage having a second differential input. The first and second stages are configured to operate in a push-pull mode to provide an output signal at a current conveyer output between the first stage and the second stage. The apparatus has a first frequency mixer configured to generate a first mixer signal based on an input signal and an oscillator signal having a first frequency. The first frequency mixer is configured to provide the first mixer signal to the first differential input. The apparatus has a second frequency mixer configured to generate a second mixer signal based on the input signal and a second oscillator signal having the first frequency. The second frequency mixer is configured to provide the second mixer signal to the second differential input.