Apparatuses, systems, and methods for implementing a multi-driver architecture are described. The multi-driver architecture may include a first driver and a second driver configured to receive an input voltage. A predriver logic circuit may select one of the first driver and the second driver to convert the input voltage into an output voltage. A controller may be connected to the first driver and the second driver, and a switch may be connected between an output terminal of the first driver and the controller. The controller may be configured to control an internal resistance of the switch. In response to the first driver being selected by the predriver logic circuit, the first driver may output the output voltage at a constant impedance level.

Disclosed are systems for adjusting bias power provided to a radio-frequency amplifier to one or more figures of merit based on sensed characteristics of the amplifier and/or characteristics of the input or output power. The systems may be used in terrestrial and satellite based communications and radar, among other possibilities.

According to one aspect, an integrated circuit having a radio frequency amplifier includes at least two amplifier stages and an impedance matching device between two amplifier stages of the radio frequency amplifier. The matching device includes two lines which are coupled by electromagnetic induction. The first line is connected to an output of the first amplifier stage and the second line is connected to an input of the second amplifier stage.

A radio-frequency module includes a module substrate, a power amplifier, and a control circuit configured to control the power amplifier. The control circuit includes a temperature sensor. The power amplifier and the control circuit are stacked one on top of another on a principal surface of the module substrate.

The present invention provides a circuitry applied to multiple power domains, wherein the circuitry includes a first circuit block and second circuit block, the first circuit block is powered by a first supply voltage of a first power domain, and the second circuit block is powered by a second supply voltage of a second power domain. The first circuit block includes a first amplifier and a switching circuit. The first amplifier is configured to receive an input signal to generate a processed input signal. When the second circuit block is powered by the second supply voltage, the switching circuit is configured to forward the processed input signal to the second circuit block; and when the second circuit block is not powered by the second supply voltage, the switching circuit disconnects a path between the first amplifier and the second circuit block.

A power supply for a radio-frequency power amplifier includes: first and second linear circuits, configured to linearly amplify a low-power signal and a high-power signal in a first envelope signal respectively and provide first and second voltages to the radio-frequency power amplifier respectively, wherein the low-power signal is a signal with a power ratio less than or equal to 30% in the envelope signal, and the high-power signal other than the low-power signal is a signal with a power ratio greater than or equal to 70% in the envelope signal; and a third circuit, configured to detect the linearly-amplified high-power signal and work in a constant on time control mode having a constant on time or a constant off time control mode having a constant off time so as to provide a third electric current to the radio-frequency power amplifier according to the detected linearly-amplified high-power signal.

This application discloses a wireless communication apparatus and a signal processing method. The wireless communication apparatus includes a power amplifier and a bias circuit. The power amplifier includes a signal input port, a signal output port, a power supply port, and a bias port. The power amplifier is configured to: receive a power supply signal through the power supply port, receive a bias signal through the bias port, receive a radio frequency signal through the signal input port, and output a power amplified radio frequency signal. The bias circuit is configured to generate the bias signal. A timing feature of the bias signal is synchronized with a timing feature of a switch signal of a power amplifier, to compensate for a nonlinear change in the TDD scenario.

An amplifier circuit includes an amplifier and a bias circuit. The bias circuit includes a bias transistor having a base terminal and a collector terminal, a transistor having a gate terminal, a source terminal, and a drain terminal, a transistor having a gate terminal, a source terminal, and a drain terminal, resistors, and a current source. The source terminals are connected to a power source. One end portion of the resistor is connected to the base terminal, the other end portion of the resistor is connected to the drain terminal, one end portion of the resistor is connected to the other end portion of the resistor, the other end portion of the resistor is connected to the bias output terminal, and the bias circuit further includes a feedback circuit that controls the electric potential of the base terminal based on the electric potential of the collector terminal.

A radio frequency module is provided that includes a plurality of power amplifiers, an external connection terminal, a filter, and a switch. The amplifiers include a first power amplifier and a second power amplifier. The external connection terminal is connected to a tracker component configured to supply a power supply voltage to the power amplifiers. Moreover, the filter is not disposed on a first path between the external connection terminal and the first power amplifier, but instead it is disposed on a second path between the external connection terminal and the second power amplifier. The switch is configured to switch connection to the external connection terminal between the first path and the second path.

A receiver front end (300) having low noise amplifiers (LNAs) is disclosed herein. A cascode having a “common source” configured input FET and a “common gate” configured output FET can be turned on or off using the gate of the output FET. A first switch (235) is provided that allows a connection to be either established or broken between the source terminal of the input FET of each LNA. A drain switch (260) is provided between the drain terminals of input FETs to place the input FETs in parallel. This increases the g.sub.m of the input stage of the amplifier, thus improving the noise figure of the amplifier.