H03F1/0261

Current control circuit and power amplifier circuit

A current control circuit controls a base current of a first transistor included in a bias circuit outputting a bias current to a power amplifier based on a base-collector voltage of the first transistor. The current control circuit includes a first circuit that outputs a signal associated with the base-collector voltage of the first transistor, and a second circuit that, based on the signal, provides electrical continuity between a base of the first transistor and a reference potential.

APPARATUS FOR OPTIMIZED TURN-OFF OF A CASCODE AMPLIFIER
20230086201 · 2023-03-23 · ·

An apparatus for turning off a cascode amplifier having a common-gate transistor and a common-source transistor is disclosed that includes the cascode amplifier, a feedback circuit, and a bias circuit. The feedback circuit is configured to receive a drain-voltage from the drain of the common-source transistor when the common-source transistor is switched to a first OFF state and produce a first feedback signal. The drain-voltage is equal to a source voltage of the common-gate transistor and the drain-voltage increases in response to switching the common-source transistor to the first OFF state. The bias circuit is configured to receive the first feedback signal and produce a bias-voltage. A first gate-voltage is produced from the bias-voltage. The cascode amplifier is configured to receive the first gate-voltage and a second gate-voltage. The common-gate transistor is configured to switch to a second OFF state in response to receiving the second gate-voltage.

BIAS CIRCUIT, AMPLIFIER, AND BIAS VOLTAGE CONTROLLING METHOD
20220352856 · 2022-11-03 · ·

A bias circuit according to an example embodiment includes a first power source configured to generate a first gate voltage that puts an amplifying transistor in an on state; a voltage generating circuit configured to generate a second gate voltage by use of the first gate voltage input from the first power source, the second gate voltage putting the amplifying transistor in an off state; a first switching circuit configured to switch between the first gate voltage input to a first input terminal and the second gate voltage input to a second input terminal and to output the first gate voltage or the second gate voltage, based on a changeover signal related to on/off control of the amplifying transistor; and a voltage output terminal configured to output the gate voltage output from the first switching circuit to the amplifying transistor.

Bias Compensation Circuit of Amplifier
20220350359 · 2022-11-03 · ·

The present invention discloses a bias compensation circuit. The bias compensation circuit includes a detecting circuit, including a diode-connected transistor circuit, with a first end for receiving a first current, and a second end coupled to a first reference voltage end; and a first diode circuit, with a first end for receiving a second current, and a second end coupled to the first reference voltage end; wherein the detecting circuit provides a first voltage level according to the diode-connected transistor circuit, and provides a second voltage level according to the first diode circuit; a voltage-current converting circuit, coupled to the detecting circuit, for generating a first reference current according to the first voltage level and the second voltage level; and a bias circuit, coupled to the voltage-current converting circuit, for receiving the first reference current, to provide a bias voltage level according to the first reference current.

ERROR VALUE MAGNITUDE DETECTOR FOR WIRELESS TRANSMITTER
20230085876 · 2023-03-23 ·

An amplifier of a transmitter includes an input that receives an input signal and generates an amplified signal at an output. A digital power meter is coupled to the input of the amplifier, generates an estimated amplified signal, and determines peak and average powers of the estimated amplified signal. An output power detector coupled to the output of the amplifier determines peak and average powers of the amplified signal. A controller coupled to the digital power meter and the output power detector determines an estimated crest factor based on the peak and average powers of the estimated amplified signal, an amplified crest factor based on the peak and average powers of the amplified signal, and an error vector magnitude based on the estimated and amplified crest factors. The controller, which is also coupled to the amplifier, then adjusts operation of the amplifier based on the error vector magnitude.

C-PHY RECEIVER WITH SELF-REGULATED COMMON MODE SERVO LOOP
20230087897 · 2023-03-23 ·

A receiving apparatus includes a terminating network for a three-wire serial bus and a feedback circuit. Each wire of the three-wire serial bus may be coupled through a resistance to a common node of the terminating network. The feedback circuit has a first amplifier circuit having an input coupled to the common node, a comparator that receives an output of the first amplifier circuit as a first input and a reference voltage as a second input, and a second amplifier circuit responsive to an output of the comparator and configured to inject a current through the common node.

Programmable optimized band switching LNA
11611319 · 2023-03-21 · ·

A front end module (FEM) integrated circuit (IC) architecture that uses the same LNA in each of several frequency bands extending over a wide frequency range. In some embodiments, switched impedance circuits distributed throughout the front end circuit allow selection of the frequency response and impedances that are optimized for particular performance parameters targeted for a desired device characteristic. Such switched impedance circuits tune the output and input impedance match and adjust the gain of the LNA for specific operating frequencies and gain targets. In addition, adjustments to the bias of the LNA can be used to optimize performance trade-offs between the total direct current (DC) power dissipated versus radio frequency (RF) performance. By selecting appropriate impedances throughout the circuit using switched impedance circuits, the LNA can be selectively tuned to operate optimally at a selected bias for operation within selected frequency bands.

APPARATUS AND METHODS FOR DETECTING AND CLAMPING POWER OF A POWER AMPLIFIER
20230079623 · 2023-03-16 ·

Apparatus and method for detecting and clamping power of a power amplifier are disclosed. In certain embodiments, a power amplifier system includes a power amplifier that amplifies a radio frequency input signal to generate a radio frequency output signal, a bias circuit that controls a bias of the power amplifier, a radio frequency coupler that generates a radio frequency coupled signal based on the radio frequency output signal, a clamp that selectively clamps the bias of the power amplifier, and a power detector that controls the clamp based on the radio frequency coupled signal.

Devices and methods for detecting a saturation condition of a power amplifier

The present disclosure relates to devices and methods for detecting and preventing occurrence of a saturation state in a power amplifier. A power amplifier module can include a power amplifier including a cascode transistor pair. The cascode transistor pair can include a first transistor and a second transistor. The power amplifier module can include a current comparator configured to compare a first base current of the first transistor and a second base current of the second transistor to obtain a comparison value. The power amplifier module can include a saturation controller configured to supply a reference signal to an impedance matching network based on the comparison value. The impedance matching network can be configured to modify a load impedance of a load line in electrical communication with the power amplifier based at least in part on the reference signal.