An amplifier comprises a common emitter stage coupled to a first and a second input, a common base stage coupled to the common emitter stage and to a first and a second output, and a cancellation path coupled to the common emitter stage and the common base stage and to the first and second outputs. The cancellation path generates a first cancellation signal that is 180 degrees out of phase with a first leakage signal at the first output and a second cancellation signal that is 180 degrees out of phase with a second leakage signal at the second output. The cancellation path comprises a first cancellation transistor coupled to the common emitter stage and the common base stage and to the first output and a second cancellation transistor coupled to the common emitter stage and the common base stage and to the second output.

Power amplifier having staggered cascode layout for enhanced thermal ruggedness. In some embodiments, a radio-frequency (RF) amplifier such as a power amplifier (PA) can be configured to receive and amplify an RF signal. The PA can include an array of cascoded devices connected electrically parallel between an input node and an output node. Each cascoded device can include a common emitter transistor and a common base transistor arranged in a cascode configuration. The array can be configured such that the common base transistors are positioned in a staggered orientation relative to each other.

A high-frequency signal amplifier circuit is used in a front-end circuit configured to propagate a high-frequency transmission signal and a high-frequency reception signal, and includes an amplifier transistor configured to amplify the high-frequency transmission signal; a bias circuit configured to supply a bias to a signal input end of the amplifier transistor; and a ferrite bead, one end of which is connected to a bias output end of the bias circuit and the other end of which is connected to the signal input end of the amplifier transistor, having characteristics in which impedance in a difference frequency band between the high-frequency transmission signal and the high-frequency reception signal is higher than impedance in DC.

A device includes: a transistor having an input terminal configured to receive an input signal and to amplify the input signal; a bias current source configured to set a bias current of the input terminal of the transistor, the bias current source having a control input for receiving a control signal for selecting the bias current to have one of a plurality of selectable bias current levels; a bias resistance connected between the bias current source and the input terminal of the transistor; a bypass switch for selectively bypassing a first part of the bias resistance; and a control circuit for controlling the bypass switch to bypass the part of the bias resistance for a predefined time period in response to a change in the bias current level, and for controlling the bypass switch to stop bypassing the first part of the bias resistance after the predefined time period expires.

A power-adjustable RF (radio frequency) output circuit is disclosed, which includes a RF frequency source transformer, wherein: one output end of the RF frequency source transformer is connected with a gate of a power amplifier module, another output end of the RF frequency source transformer is connected with a gate bias voltage control circuit; a source of the power amplifier module is connected with ground; the gate of the power amplifier module is connected with a resistor which is connected with ground, a drain of the power amplifier module is connected with a fixed voltage DC (direct current) power supply and also connected with a RF filtering network for outputting a RF power through the RF filtering network.

Distributed amplifiers with controllable linearization are provided herein. In certain embodiments, a distributed amplifier includes a differential input transmission line, a differential output transmission line, and a plurality of differential distributed amplifier stages connected between the differential input transmission line and the differential output transmission line at different points or nodes. The distributed amplifier further includes a differential non-linearity cancellation stage connected between the differential input transmission line and the differential output transmission line and providing signal inversion relative to the differential distributed amplifier stages. The differential non-linearity cancellation stage operates with a separately controllable bias from the differential distributed amplifier stages, thereby providing a mechanism to control the linearity of the distributed amplifier.

Power consumption of a signal processing circuit is reduced. Further, power consumption of a semiconductor device including the signal processing circuit is reduced. The signal processing circuit includes a reference voltage generation circuit, a voltage divider circuit, an operational amplifier, a bias circuit for supplying bias current to the operational amplifier, and first and second holding circuits. The first holding circuit is connected between the reference voltage generation circuit and the bias circuit. The second holding circuit is connected between the voltage divider circuit and a non-inverting input terminal of the operational amplifier. Reference voltage from the reference voltage generation circuit and reference voltage from the voltage divider circuit can be held in the first and second holding circuits, respectively, so that the reference voltage generation circuit can stop operating. Thus, power consumption of the reference voltage generation circuit can be reduced.

In accordance with an embodiment, a circuit includes a low noise amplifier transistor disposed on a first integrated circuit, a single pole multi throw (SPMT) switch disposed on a second integrated circuit, and a bypass switch coupled between a control node of the low noise amplifier transistor and an output node of the low noise amplifier transistor. The SPMT switch couples a plurality of module input terminals to a control node of the low noise amplifier transistor, and the bypass switch including a first switch coupled between the control node of the low noise amplifier transistor and an intermediate node, a second switch coupled between the intermediate node and the output node of the low noise amplifier transistor, and a third switch coupled between the intermediate node and a first reference node. The first integrated circuit and the second integrated circuit are disposed on a substrate.

Provided are a gain compensation device and a bias circuit device. A compensation bias current is generated by the gain compensation device to compensate the gain deviation of power amplifier and improve stability of power amplifier. Through high-temperature compensation unit and low-temperature compensation unit in different gears, gain of power amplifier is compensated along with temperature changes, thereby improving feasibility of the gain compensation device. It takes small space, and the circuit only includes the circuits corresponding to high-temperature compensation unit and low-temperature compensation unit, so the circuit is relatively simple and beneficial to miniaturization. In the bias circuit device, based on an initial bias current provided by a bandgap reference, the gain compensation device is added to generate a compensation bias current, and the initial bias current and compensation bias current are superimposed, so that the gain of power amplifier is further compensated, which improves stability of power amplifier.

A phase shift circuitry includes: a signal generation circuitry that receives an input signal, and outputs four signals different in phase from each other by 90 degrees based on the input signal, the four signals includes a first signal and a second signal; four variable amplifier circuitry that each includes a transistor, and amplify the four signals individually, with amplification factors based on control voltages supplied to gates of the transistors, the four variable amplifier circuitry include a first amplifier amplifies the first signal by a first control voltage and a second amplifier amplifies the second signal by a second control voltage; a synthetic circuitry that synthesizes output signals of the four variable amplifier circuitry, and outputs a synthesized signal; and a control circuitry supplies voltages, that are equal to or higher than the gate threshold value, to the first amplifier and the second amplifier.