Apparatus and methods for a bias supply circuit to support power supply including a switched-mode voltage converter cascaded with an n-channel-based linear regulator are provided. In an example, a cascaded power supply system can include a switched-mode DC-to-DC power converter, including an input voltage node, a first stage output voltage node, and a bootstrapped floating bias voltage node, and a linear regulator circuit. The linear regulator circuit can include an n-channel field-effect transistor (NFET) pass transistor, including a drain terminal coupled to the first stage output voltage node, a gate terminal, and a source terminal configured to provide a second-stage output voltage, and a gate driver circuit, including a driver output coupled to the gate terminal of the NFET pass transistor, and a high side supply node configured to receive a bias voltage generated from the bootstrapped floating bias voltage node.

Devices and methods related to embedded sensors for dynamic error vector magnitude corrections. In some embodiments, a power amplifier (PA) can include a PA die and an amplification stage implemented on the PA die. The amplification stage can include an array of amplification transistors, with the array being configured to receive and amplify a radio-frequency (RF) signal. The PA can further include a sensor implemented on the PA die. The sensor can be positioned relative to the array of amplification transistors to allow sensing of an operating condition representative of at least some of the amplification transistors. The sensor can be substantially isolated from the RF signal.

A communication device includes a power amplifier that generates power signals according to one or more operating bands of communication data, with the amplitude being driven and generated in output stages of the power amplifier. The final stage can include an output passive network that suppresses suppress an amplitude modulation-to-phase modulation (AM-PM) distortion. During a back-off power mode a bias of a capacitive unit of the output power network component can be adjusted to minimize an overall capacitance variation. A output passive network can further generate a flat-phase response between dual resonances of operation.

A temperature compensation circuit for a power amplifier is provided, wherein data of circuit configurations corresponding to specific temperatures (including data associated with an output terminal voltage, a bias voltage, an adaptive bias, and a matching impedance of the power amplifier) for the power amplifier is stored in a read-only memory. Therefore, the temperature compensation circuit is capable of reading the data according to a temperature sensing signal to adjust the circuit configuration of the power amplifier accordingly, thereby, in a case of a constant input power of the power amplifier, an output power variance of the power amplifier is within a second interval (e.g., −10%˜+10%) when an environment temperature varies within a first interval. Therefore, the power amplifier has a stable gain.

A power amplifier module includes a first power amplifier that amplifies an input signal and outputs a first transmission signal; a first switch circuit that receives input of the first transmission signal and performs switching to, of a plurality of signal paths, a signal path through which the first transmission signal passes; and a second switch circuit that receives input of the first transmission signal output from the first switch circuit through the signal path to which the first switch circuit has performed switching and switches between signal paths to an antenna terminal. The second switch circuit includes a power supply circuit that supplies a reference voltage to the first switch circuit and the second switch circuit.

A power amplifier for a radio frequency transceiver including a driver, a disable circuit, and a bias circuit. The driver includes a source node for receiving a drive voltage when enabled and includes an output node that is susceptible to strong blocker signals when disabled. The bias circuit includes first and second bias nodes for driving the voltage level of the source and output nodes, respectively, to suitable bias voltage levels to minimize impact of blocker signals. The disable circuit includes switch circuits to couple the driver to the bias circuit in the disable mode. The bias circuit may include at least one voltage source. The bias circuit may be coupled to a supply voltage and may include a voltage divider coupled between the source and output nodes. The bias circuit may include a source-follower circuit to isolate the bias voltages from variations of the supply voltage.

A transceiver includes a medium dependent interface configured to provide AC (alternate current) coupling between a first node and a second node; a broadband matching network 120 configured to couple the second node to a third node; a programmable gain amplifier configured to receive a third voltage signal at the third node and output a fourth voltage signal in accordance with a first logical signal; an analog-to-digital converter configured to receive the fourth voltage signal and output a first data in accordance with the first logical signal and a first clock; and a digital-to-analog converter configured to receive a second data and output a first current signal to the third node in accordance with a second logical signal and a second clock, wherein: the first logical signal and the second logical signal are asserted alternately.

Various methods and circuital arrangements for biasing one or more gates of stacked transistors of an amplifier are presented, where the amplifier can have a varying supply voltage. According to one aspect, the gate of the input transistor of the amplifier is biased with a fixed voltage whereas the gates of the other transistors of the amplifier are biased with variable voltages that are linear functions of the varying supply voltage. According to another aspect, the linear functions are such that the variable voltages coincide with the fixed voltage at a value of the varying supply voltage for which the input transistor is at the edge of triode. According to another aspect, biasing of the stacked transistors is such that, while the supply voltage varies, the drain-to-source voltage of the input transistor is maintained to a fixed value whereas the drain-to-source voltages of all other transistors are equal to one another.

An amplifier device includes a regulator circuit, a first voltage converting circuit, a first control circuit, and an amplifier circuit. The regulator circuit is configured to output a first driving voltage. The first voltage converting circuit is coupled to the regulator circuit, and is configured to output one of the first driving voltage and at least one first voltages related to the first driving voltage, as a first operating voltage. The first control circuit is coupled to the first voltage converting circuit through a first node, and is configured to receive the first operating voltage and generate a first operating signal according to the first operating voltage and a first control signal. The amplifier circuit is coupled to the first control circuit and the regulator circuit, and is configured to receive the first driving voltage, and is controlled by the first operating signal to generate an output voltage.

A power amplifier circuit includes power amplifiers connected in stages to amplify a high-frequency input signal and to output an amplified high-frequency output signal, bias circuits each of which outputs a bias current to a corresponding one of the power amplifiers, and a bias control circuit configured to output a bias control current based on a second reference potential that varies in response to power of the high-frequency output signal and that is a potential of a portion in one bias circuit of the bias circuits to one or more bias circuits in a stage preceding the one bias circuit for increasing a bias current outputted from the one or more bias circuits in the stage preceding the one bias circuit.