An outphasing amplifier having: a first branch arranged to receive and process a first branch signal, the first branch signal being phase modulated, with constant amplitude envelope; and a second branch arranged to receive and process a second branch signal, the second branch signal being phase modulated, with constant amplitude envelope, and at least a portion of the second branch signal anti-phase from the first branch signal, wherein each branch includes: circuitry arranged to process the signal to reduce the energy in sidebands of the signal away from the central frequency, while retaining the phase information in the signal; and an amplifier arranged to amplify the filtered and re-asserted branch signal.

Aspects of the subject disclosure may include, for example, a wireless power receiver configured to receive a wireless power signal from a power transmitting unit. A wireless radio unit is configured to communicate with the power transmitting unit. A controllable rectifier circuit is configured to rectify the wireless power signal. The controllable rectifier circuit can include a rectifier configured to generate a rectified voltage from the wireless power signal, based on switch control signals. A rectifier control circuit is configured to generate the switch control signals and to generate first control data that indicates a first rectifier duty cycle of the switch control signals. The wireless radio unit sends the first control data to the power transmitting unit. Other embodiments are disclosed.

The application provides a radio frequency circuit, including: a first circuit and a second circuit. The first circuit is configured to receive a first signal and a second signal; split the first signal into a third signal and a fourth signal, and split the second signal into a fifth signal and a sixth signal; adjust a phase of the fifth signal to obtain a seventh signal; and combine the seventh signal and the third signal into an eighth signal. The second circuit includes a primary power amplifier branch and a secondary power amplifier branch, and the primary power amplifier branch is configured to process the fourth signal and the sixth signal, and the secondary power amplifier branch is configured to process the eighth signal.

An inverted three-stage Doherty amplifier is disclosed. The amplifier provides an input power divider, a carrier amplifier, two peak amplifiers, and an output combiner. The output combiner includes five quarter-wavelength (/4) lines, three of which correspond to three amplifiers, one of rest two /4 lines combines an output of the carrier amplifier with an output of the first peak amplifier, the last /4 line combines the combined output of the carrier amplifier and the first peak amplifier with an output of the second peak amplifier. The five /4 lines have respective impedance to optionally adjust output impedance of the respective amplifiers.

An apparatus for quantized linear amplification with nonlinear amplifiers that performs a linear amplification of variable-envelope single carrier (SC) or multi-carrier (MC) bandpass signals, based on sampled and quantized versions of its complex envelope, where the quantizer generates N.sub.b bits that are mapped into N.sub.mN.sub.b polar components, in which the quantized symbol can be decomposed, that are modulated as N.sub.m constant or quasi constant envelope signals and where each one is amplified by a nonlinear amplifier.

An apparatus for quantized linear amplification with nonlinear amplifiers that performs a linear amplification of variable-envelope single carrier (SC) or multi-carrier (MC) bandpass signals, based on sampled and quantized versions of its complex envelope, where the quantizer generates N.sub.b bits that are mapped into N.sub.mN.sub.b polar components, in which the quantized symbol can be decomposed, that are modulated as N.sub.m constant or quasi constant envelope signals and where each one is amplified by a nonlinear amplifier.

A technique that reduces or eliminates trading-off power amplifier efficiency and costly external filtering in amplitude and phase modulated sinusoidal signal generation uses multi-phase outphasing and a multi-phase switching mode power amplifier to generate the amplitude and phase modulated sinusoidal signals. The technique combines multiple clock phases with sinusoidally weighted circuits of the switching mode power amplifier to improve amplitude and phase modulated sinusoidal signal generation.

An embodiment provides an amplifier system with multiple amplification paths connected to a combiner for combination of signals amplified in the amplification paths, each amplification path comprising an amplifier and a matching network provided between the amplifier and the combiner, wherein the individual amplifiers can interact through the combiner, causing an active load-pull effect. The matching networks of the paths comprise harmonic terminations configured to one or more of reduce an overlap between the voltage and current waveforms within the amplifier connected to the matching network and improve the linearity of one or more of the amplifiers.

An amplifier includes a signal acquiring unit that acquires an input signal, which is a digital signal, a signal generation unit that generates an in-phase signal, an orthogonal signal, and an envelope signal by using the input signal, and a signal distribution unit that generates a first signal and a second signal by using the in-phase signal, the orthogonal signal, and the envelope signal, a differential value of a function representing either or both an amplitude ratio and a phase difference is continuous during transition of the envelope signal from a minimum value to a maximum value.

Described herein are power amplifier (PA) architectures that improve PA performance (e.g., efficiency, linearity, etc.) over an extended range of the operating power levels of the PA. These architectures can be implemented on a single chip to provide a single-chip standalone PA solution. This improvement comes with little additional complexity, little additional current consumption, and/or little additional chip area. The architectures utilize a dynamic biasing technique using positive envelope feedback based at least in part on an instantaneous envelope signal at an output of a power amplifier.