Circuits and methods for use in amplifying amplitude and phase modulated signals. A circuit uses a digital controlled multi stage combiner, a signal phase discrete mapper and a combiner digital control circuit with N parallel signal feeding it. The signals resulting from N power amplifiers have phases with belonging to an alphabet with M discrete phases prior to being fed to the multi stage combiner. The phases of the N input signals are converted in an control signal generator into Ns sets of digital control signals to control N.M sets of switches where the signals are selected according the phase and sent to the corresponding combiner in the M possible combiners. Each one combiner from the set of M combiner then combines these signals. A second stage with digital controlled combiner, combines into two sub-sets of signals the signals resulting from first stage and the resulting outputs of the combiner are then combined by a third combining digital controlled stage into the output signal. The signal amplifiers employed before the combining stage may be Class Dor Class F amplifiers to provide high efficiency amplification of the signals.

A first branch group circuit includes a first branch circuit receiving a first RF input signal and first control information; and a second branch circuit receiving the first input signal and second control information. Each of the first and second branch circuits includes a power amplifier. The second control information enables the second branch circuit to be switched on or off while the first branch circuit remains on. A second branch group circuit includes: a third branch circuit receiving a second RF input signal and third control information; and a fourth branch circuit receiving the second input signal and fourth control information. Each of the third and fourth branch circuits includes a power amplifier. The fourth control information enables the fourth branch circuit to be switched on or off while the third branch circuit remains on. A combiner combines output signals of the power amplifiers to produce an output signal.

An embodiment electronic device comprises at least two antennas for transmitting signals, and at least one transmission path, the transmission path including a first coupling stage including a power divider, variable-gain power amplifiers, and a second coupling stage including a power combiner. Each coupling stage includes two inputs and two outputs, the two inputs of the first coupling stage being configured to receive a power input signal. Each output of the first coupling stage is connected to a different input of the second coupling stage via the variable-gain power amplifiers, and each output of the second coupling stage is connected to a different antenna. A controller is configured to control the gains of the variable-gain power amplifiers according to the characteristics of the power input signal, the signals transmitted by the antennas, and the coupling stages.

Embodiments of this application disclose a signal processing circuit, a radio frequency signal transmitter, and a communications device, and relate to the field of electronic device technologies, to improve power amplification efficiency of the signal processing circuit. The signal processing circuit includes: a splitter, a radio frequency signal converter, a first branch power amplifier, a second branch power amplifier, and a combiner. The splitter is connected to the radio frequency signal converter, the radio frequency signal converter is connected to the first branch power amplifier and the second branch power amplifier, and the first branch power amplifier and the second branch power amplifier are connected to the combiner.

A circuit includes a transformer having a primary coil coupled to a first power amplifier (PA) and a second PA, and a secondary coil. The secondary coil supplies a current to an antenna based on a first direction of a first phase of a first amplified constant-envelope signal in the primary coil with respect to a second phase of a second amplified constant-envelope signal in the primary coil. The circuit further includes load impedance coupled between a median point of the primary coil and ground. The load impedance is adjusted to match one of an impedance of the differential antenna, an impedance of the first PA, and an impedance of the second PA, based on the ripples detected by the ripple detector.

A common-mode rejection receiver including a first differential amplifier arranged to receive a differential signal including receiving a positive signal of the differential signal at a first non-inverting input port and receiving a negative signal of the differential signal at a first inverting input port, and output a first differentiated signal based on a voltage differential between the positive signal and the negative signal. A clamping circuit is arranged to limit a magnitude of the first differentiated signal to a pre-determined limit. A second differential amplifier is arranged to receive the positive signal at a second inverting input port and receive the negative signal at a second non-inverting input port, and output a second differentiated signal. A matching circuit is arranged to receive the second differentiated signal output and output a matched signal. A summing circuit adds the clamped signal and matched signal and outputs a receiver output signal.

A circuit includes a transformer having a primary coil coupled to a first power amplifier (PA) and a second PA, and a secondary coil. The secondary coil supplies a current to an antenna based on a first direction of a first phase of a first amplified constant-envelope signal in the primary coil with respect to a second phase of a second amplified constant-envelope signal in the primary coil. The circuit further includes load impedance coupled between a median point of the primary coil and ground. The load impedance dissipates the current based on a second direction of the first phase of the first amplified constant-envelope signal in the primary coil with respect to the second phase of the second amplified constant-envelope signal in the primary coil, which results in improved power efficiency.

A common-mode rejection receiver including a first differential amplifier arranged to receive a differential signal including receiving a positive signal of the differential signal at a first non-inverting input port and receiving a negative signal of the differential signal at a first inverting input port, and output a first differentiated signal based on a voltage differential between the positive signal and the negative signal. A clamping circuit is arranged to limit a magnitude of the first differentiated signal to a pre-determined limit. A second differential amplifier is arranged to receive the positive signal at a second inverting input port and receive the negative signal at a second non-inverting input port, and output a second differentiated signal. A matching circuit is arranged to receive the second differentiated signal output and output a matched signal. A summing circuit adds the clamped signal and matched signal and outputs a receiver output signal.

A signal processing system includes n paths of load modulation modules and a combination module, where then paths of load modulation modules are connected in parallel, an output end of each path of load modulation module is connected to an input end of the combination module, and n is an integer greater than 1; the n paths of load modulation modules include one path of main power amplification module and (n-1) paths of auxiliary power amplification modules, and the auxiliary power amplification modules are turned on when power values of signals received by input ends of the load modulation modules are greater than a first threshold; and the main power amplification module includes two outphasing power amplification units, and each path of auxiliary power amplification module includes two outphasing power amplifier arrays or one digital polar power amplifier array.

A system may include a first power detector to measure a power level of a signal on a first transmitter channel, a second power detector to measure a power level of a signal on a second transmitter channel. The system may include a combiner to provide a combined signal associated with the signal on the first transmitter channel and the signal on the second transmitter channel, and a third power detector to measure a power level of the combined signal. The system may include a processing circuit to determine a relative phase difference between the signal on the first transmitter channel and the signal on the second transmitter channel based on results of measuring the power level of the signal on the first transmitter channel, measuring the power level of the signal on the second transmitter channel, and measuring the power level of the combined signal.