Methods and apparatuses for controlling gain of a single stage cascode FET amplifier are presented. According to one aspect, a series-connected resistor and capacitor is coupled to a gate of a cascode FET transistor of the amplifier, the capacitor providing a short at frequencies of operation of the amplifier. According to another aspect, values of the resistor can be used to control gain of the amplifier. According to yet another aspect, the resistor is a variable resistor whose value can be controlled/adjusted to provide different gains of the amplifier according to a linear function of the resistor value. An input matching network coupled to an input of the amplifier can be used to compensate for different noise figure degradations from different values of the resistor.

Provided are a low noise amplifier and a receiver. The low noise amplifier comprises at least one input port configured to receive an input signal including a carrier, first to third output ports connected to first to third load circuits, respectively, and configured to transmit an output signal, a first amplifier stage comprising a first type gain stage connected to the input port and first to third first type drive stages connected to the first to third output ports, respectively and second to third amplifier stages, each comprising a second type gain stage and a second type drive stage, wherein the low noise amplifier is configured to vary an impedance of an input transistor included in each of the first type gain stage and the second type gain stage, so that an input impedance is uniform even when operating in a plurality of operation modes.

Various embodiments of the present technology may provide methods and apparatus for a track-and-hold amplifier configured to sample and amplify an analog signal. Methods and apparatus for a track-and-hold amplifier according to various aspects of the present invention may provide an isolation circuit configured to isolate transient current in a track-and-hold capacitor during a track phase. According to various embodiments, selective activation of the isolation circuit provides a settling time that is independent of the gain of the amplifier.

Circuits and methods for generating a bypass pulse to an RF circuit that increases the response time of the circuit to mode changes. Embodiments include a pulse generation circuit that it is self-initiated and self-terminated, generating a bypass pulse as a function of voltages V1 and V2 along a signal path. Voltage V3, a scaled version of V1, is compared to a voltage V4 derived from V2 and a pulse is output while V3>V4. The pulse temporarily lowers the signal path impedance, reducing the RC time constant of the signal path and allowing fast charging of components coupled to the signal path. The pulse may be used with any other circuit that needs a faster settling time after a mode change but is slowed down by an RC time constant. Usage also extends to providing for rapid discharge of the signal path by adding additional logic components.

Methods and devices to implement efficiently an AUX terminal in RF front end receivers using LNAs are described. The described methods implement a smaller number of switches resulting in an overall performance improvement by reducing the noise figure at the input of the LNA. The presented devices can be used in low/high gain and bypass modes and can accommodate an arbitrary number of bands over a wide frequency range.

In one embodiment, a dual-mode power amplifier that can operate in different modes includes: a first pair of metal oxide semiconductor field effect transistors (MOSFETs) to receive and pass a constant envelope signal; a second pair of MOSFETs to receive and pass a variable envelope signal, where first terminals of the first pair of MOSFETs are coupled to first terminals of the second pair of MOSFETs, and second terminals of the first pair of MOSFETs are coupled to. second terminals of the second pair of MOSFETs; and a shared MOSFET stack coupled to the first pair of MOSFETs and the second pair of MOSFETs.

An amplifier and corresponding method include a field-effect transistor (FET) amplifier and a cascode FET. Each FET may operate with a positive ratio between its third-order nonlinearity coefficient and its linear gain. An inductor added at a gate of the cascode FET, operatively coupled with other components in a circuit, results in a first equivalent impedance looking into an input of the cascode FET. The first equivalent impedance may substantially offset a distortion output of the FET amplifier based upon the added inductor. The inductor operatively coupled with the circuit may result in a second equivalent impedance looking out of the gate of the cascode FET. The second equivalent impedance may substantially offset a distortion output of the cascode FET based upon the added inductor. In addition, a programmable capacitor connected between the gate and drain of the cascode FET may further substantially offset a distortion output of each FET.

In one embodiment, a dual-mode power amplifier that can operate in different modes includes: a first pair of metal oxide semiconductor field effect transistors (MOSFETs) to receive and pass a constant envelope signal; a second pair of MOSFETs to receive and pass a variable envelope signal, where first terminals of the first pair of MOSFETs are coupled to first terminals of the second pair of MOSFETs, and second terminals of the first pair of MOSFETs are coupled to. second terminals of the second pair of MOSFETs; and a shared MOSFET stack coupled to the first pair of MOSFETs and the second pair of MOSFETs.

Methods and apparatus for an amplifier including first and second transistors coupled in a stacked configuration with first and second current mirrors to provide respective bias signals to the amplifier transistors. A reference transistor is coupled to the first and second current mirrors for referencing the bias signals together.

An apparatus includes an amplifier and a first inductor coupled to an input of the amplifier. The apparatus also includes a second inductor that is inductively coupled to the first inductor and that couples the amplifier to a first supply node. The apparatus further includes a third inductor that is inductively coupled to the first inductor and to the second inductor and that couples the amplifier to a second supply node.