The present disclosure relates to circuitry including an auto-bias circuit for a stacked FET power amplifier. The auto-bias circuit includes a dividing circuit and an averaging circuit. The dividing circuit is configured to receive a control signal with a control voltage and provide a first pre-gate signal having a first pre-gate voltage that corresponds to a fraction of the control voltage. The averaging circuit is configured to receive the control signal and a supply signal with a supply voltage and provide a second pre-gate signal having a second pre-gate voltage that corresponds to a fraction of a sum of the control voltage and the supply voltage. The stacked power amplifier includes a first FET in series with a second FET. The first FET receives a first gate signal derived from the first pre-gate signal. The second FET receives a second gate signal derived from the second pre-gate signal.

Methods and devices for reducing gate node instability of a differential cascode amplifier are presented. Ground return loops, and therefore corresponding parasitic inductances, are eliminated by using voltage symmetry at nodes of two cascode amplification legs of the differential cascode amplifier. Series connected capacitors are coupled between gate nodes of pairs of cascode amplifiers of the two cascode amplification legs so to create a common node connecting the two capacitors. In order to reduce peak to peak voltage variation at the common node under large signal conditions, a shunting capacitor is connected to the common node.

Various methods and circuital arrangements for biasing one or more gates of stacked transistors of an amplifier are possible where the amplifier is configured to operate in at least an active mode and a standby mode. Circuital arrangements can reduce bias circuit standby current during operation in the standby mode while allowing a quick recovery to normal operating conditions of the amplifier. Biasing an input transistor of the stacked transistors can be obtained by using a replica stack circuit.

RF receive circuitry, which includes a first output impedance matching circuit coupled to a first alpha output of a first alpha LNA, a second output impedance matching circuit coupled to a first beta output of a first beta LNA, and a first dual output RF LNA, is disclosed. The first dual output RF LNA includes the first alpha LNA, the first beta LNA, and a first gate bias control circuit, which is coupled between a first alpha input of the first alpha LNA and ground; is further coupled between a first beta input of the first beta LNA and the ground; is configured to select one of enabled and disabled of the first alpha LNA using an alpha bias signal via the first alpha input; and is further configured to select one of enabled and disabled of the first beta LNA using a beta bias signal via the first beta input.

An amplifier may include control circuitry that may track a first input signal parameter and, in response, adjust a value of a second input parameter. Input parameter tracking and adjustment may facilitate control of output parameters for the amplifier. For example, an envelope-tracking amplifier may track input signal amplitude and adjust other input parameters in response. The adjustments may facilitate control of output parameters, such as gain or efficiency. The amplifier may further include calibration circuitry to determine adjustment responses to various tracked input parameters.

An amplifier includes an input terminal for receiving an input signal, an output terminal for outputting an output signal, a first transistor, a second transistor having a first terminal coupled to a second terminal of the first transistor, a third transistor having a first terminal coupled to a second terminal of the second transistor, a capacitor coupled between a control terminal and a second terminal of the third transistor, a bias circuit coupled to the first terminal of the third transistor for providing a bias voltage to the third transistor, a fourth transistor having a first terminal coupled to the input terminal and a second terminal coupled to the output terminal for providing a bypass path, and a fifth transistor having a first terminal coupled to the first terminal of the first transistor and a second terminal coupled to the output terminal.

Multiplex modules for use in carrier aggregation receivers are disclosed. In an exemplary embodiment, an apparatus includes an LNA multiplexer configured to receive a plurality of RF signals at a plurality of input terminals and to combine the RF signals into a combined RF signal that is output from an output terminal. The apparatus also includes an LNA demultiplexer configured to receive the combined RF signal at an input port that is connected to the output terminal and to distribute the combined RF signal to a plurality of output ports.

A low noise amplifier (LNA) system for amplifying a plurality of carriers includes a first amplifier circuit that generates a first radio-frequency (RF) output signal by amplifying a first input RF signal corresponding to a first frequency band, the first amplifier circuit having a first input impedance, and a second amplifier circuit that generates a second RF output signal by amplifying the first input RF signal when the system is in a first multi-output mode, a second input impedance of the second amplifier having a first impedance value when the system is in the first multi-output mode. The LNA system further includes a first impedance controller that maintains the second input impedance of the second amplifier circuit at a second impedance value when the apparatus is in a mode other than the first multi-output mode. The second impedance value is substantially the same as the first impedance value.

A transformer includes: a primary winding comprising a first port, a second port and a metal layer connected between the first port and the second port, the metal layer comprising a plurality of sections of different electrical lengths and/or characteristic impedances; and a secondary winding electromagnetically coupled with the primary winding, the secondary winding comprising a first port, a second port and a metal layer connected between the first port and the second port, the metal layer comprising a plurality of sections of different electrical lengths and/or characteristic impedances.

An active circuit includes an active element, an input unit, and a bypass unit. The active element is coupled to an output terminal of the active circuit for outputting an output signal. The input unit is coupled to an input terminal of the active circuit, and is coupled to an input terminal of the active element through a node. The input unit adjusts a capacitance value of the input unit according to a first control signal. The bypass unit is coupled to an output terminal of the input unit through the node, and is coupled to the output terminal of the active circuit. The bypass unit turns on or off a signal bypassing path according to a second control signal.