A power amplifier circuit includes a first power amplifier, a balun, a second power amplifier, and a third power amplifier. The second and third power amplifiers each include unit bipolar transistors each including a first terminal electrically connected to a reference potential, a second terminal, and a third terminal that outputs an amplified signal; a common input terminal electrically connected to the second terminals of the transistors and receives an RF signal; a common bias terminal electrically connected to the second terminals of the transistors and receives a bias current; a common output terminal electrically connected to the third terminals of the transistors and outputs the amplified signal; and resistance elements each of which is electrically connected between the common input terminal and the second terminal of a corresponding one of the transistors and cuts a DC component of the bias current.

The present disclosure relates to systems and methods for operating transceiver circuitry to transmit or receive signals on various frequency ranges. To do so, a transmitter or a receiver of the transceiver circuitry is selectively coupled to or uncoupled from an antenna of the transceiver circuitry. Additionally, radio frequency filters may be individually or collectively coupled to and/or uncoupled from the antenna to filter different frequencies in the transmitting or receiving signals.

An amplifier may comprise first and second matching networks; first and second transistors; and a transformer including first to third inductors. Also, a gate and a source of the first transistor are connected to the first matching network, one end of the first inductor is connected to a drain of the first transistor, the other end of the first inductor is connected to a source of the second transistor, one end of the second inductor is connected to a gate of the second transistor, the other end of the second inductor is grounded, one end of the third inductor is connected to a drain of the second transistor, and the other end of the third inductor is connected to the second matching network.

An amplifier circuit is a cascade amplifier circuit that includes a first transistor circuit including a signal input portion to which a signal is input from outside; a load circuit connected between the first transistor circuit and a power-supply line; and a second transistor cascode-connected between the load circuit and the first transistor circuit. The first transistor circuit is constituted by a plurality of transistors connected in parallel, and a bias circuit is provided that selectively supplies a bias voltage to the plurality of transistors.

Composite cascode power amplifiers for envelope tracking applications are provided herein. In certain embodiments, an envelope tracking system includes a composite cascode power amplifier that amplifies a radio frequency (RF) signal and that receives power from a power amplifier supply voltage, and an envelope tracker that generates the power amplifier supply voltage based on an envelope of the RF signal. The composite cascode power amplifier includes an enhancement mode (E-MODE) field-effect transistor (FET) for amplifying the RF signal and a depletion mode (D-MODE) FET in cascode with the E-MODE FET.

A transceiver includes a medium dependent interface configured to provide AC (alternate current) coupling between a first node and a second node; a broadband matching network 120 configured to couple the second node to a third node; a programmable gain amplifier configured to receive a third voltage signal at the third node and output a fourth voltage signal in accordance with a first logical signal; an analog-to-digital converter configured to receive the fourth voltage signal and output a first data in accordance with the first logical signal and a first clock; and a digital-to-analog converter configured to receive a second data and output a first current signal to the third node in accordance with a second logical signal and a second clock, wherein: the first logical signal and the second logical signal are asserted alternately.

Amplifier having input power protection. In some embodiments, an amplifier circuit can include an input node and an output node, and an amplifier implemented between the input node and the output node. The amplifier circuit can further include a bias circuit configured to provide a bias signal to the amplifier. The amplifier circuit can further include a protection circuit configured to generate a detected voltage representative of a peak of a radio-frequency signal present at the input node. The protection circuit can be further configured to enable a protection mode when the detected voltage is greater than a first threshold value and to disable the protection mode when the detected voltage is less than a second threshold value that is less than the first threshold value.

An electronic circuit and method are provided. The electronic circuit includes an in-phase(I)-quadrature(Q) amplifier including an I cascode branch and a Q cascode branch, the IQ amplifier configured to receive a differential input and control signals, control, based on the control signals, gate voltages in the I cascode branch and gate voltages in the Q cascode branch, generate an I output signal with the I cascode branch, and generate a Q output signal with the Q cascode branch, and a quadrature coupler configured to perform quadrature summation of the I output signal and the Q output signal and generate a final phase shifted output.

An amplifier circuit configuration capable of processing non-contiguous intra-band carrier aggregate (CA) signals using amplifiers is disclosed herein. In some cases, each of a plurality of amplifiers is an amplifier configured as a cascode (i.e., a two-stage amplifier having two transistors, the first configured as a “common source” input transistor, e.g., input field effect transistor (FET), and the second configured in a “common gate” configuration as a cascode output transistor, (e.g. cascode output FET). In other embodiments, the amplifier may have additional transistors (i.e., more than two stages and/or stacked transistors). The amplifier circuit configuration can be operated in either single mode or split mode. A switchable coupling is placed between the drain of the input FETs of each amplifier within the amplifier circuit configuration. During split mode, the coupling is added to the circuit to allow some of the signal present at the drain of each input FET to be coupled to the drain of the other input FET.

An apparatus includes a radio-frequency (RF) circuit, which includes a power amplifier coupled to receive an RF input signal and to provide an RF output signal in response to a modified bias signal. The RF circuit further includes a bias path circuit coupled to modify a bias signal as a function of a characteristic of an input signal to generate the modified bias signal. The bias path circuit provides the modified bias signal to the power amplifier.