Patent classifications
H03F1/223
Source switch split LNA design with thin cascodes and high supply voltage
A receiver front end capable of receiving and processing intraband non-contiguous carrier aggregate (CA) signals using multiple low noise amplifiers (LNAs). Cascode circuits, each having a “common source” configured input FET and a “common gate” configured output FET, serve as the LNAs. An amplifier-branch control switch, configured to withstand relatively high voltage differentials by means of a relatively thick gate oxide layer and coupled between a terminal of the output FET and a power supply, controls the ON and OFF state of each LNA while enabling use of a relatively thin gate oxide layer for the output FETs, thus improving LNA performance. Some embodiments may include a split cascode amplifier and/or a power amplifier.
Amplifier
Provided is an amplifier that includes a first transistor including a gate terminal to which an applied input signal is input, where a current depending on the applied input signal flows through the first transistor. A gate terminal of a second transistor is connected to a load section, and a current depending on a change in a voltage of the drain terminal of the first transistor flows through the second transistor. A source terminal of the first transistor and a drain terminal of the second transistor are connected in common to a first resistance, and the current from the first transistor and the current from the second transistor flow through the first resistance. A third transistor supplies a current approximately equal to the current of the second transistor. The current supplied by the third transistor is output from an output end.
DOHERTY POWER AMPLIFIER
An input signal is input to a main power amplifier and an auxiliary power amplifier. A combiner is connected to an output of the main power amplifier and an output of the auxiliary power amplifier. The combiner includes an impedance converter, first and second lumped elements. The impedance converter is connected to a combining point. The first lumped element is connected between the output of the main power amplifier and the combining point. The second lumped element is connected between the output of the auxiliary power amplifier and the combining point. A line length between the output of the main power amplifier and the combining point is the same as that between a line length between the output of the auxiliary power amplifier and the combining point.
RADIO FREQUENCY POWER AMPLIFIER
According to an embodiment, An integrated circuit comprising a first cascode radio frequency (RF) power amplifier that includes a first common source transistor having a gate configured to receive a first RF signal, and a source connected to a neutral point; a first common gate transistor having a gate and a drain connected to a power source node, and a source connected to a drain of the first common source transistor; and a first resistor coupled between a bulk of the first common gate transistor and a first bulk bias node configured to provide a voltage that is greater than or equal to a voltage at the source of the first common gate transistor, wherein the first resistor is configured to obtain a floating point.
Front end systems with multi-mode power amplifier stage and overload protection of low noise amplifier
Front end systems and related devices, integrated circuits, modules, and methods are disclosed. One such front end system includes a low noise amplifier in a receive path and a multi-mode power amplifier circuit in a transmit path. An overload protection circuit can adjust an impedance of a switch coupled to the low noise amplifier based on a signal level of the low noise amplifier. The multi-mode power amplifier circuit includes a stacked output stage including a transistor stack of two or more transistors. The multi-mode power amplifier circuit also includes a bias circuit configured to control a bias of at least one transistor of the transistor stack based on a mode of the multi-mode power amplifier circuit. Other embodiments of front end systems are disclosed, along with related devices, integrated circuits, modules, methods, and components thereof.
LOW NOISE AMPLIFIERS WITH GAIN STEPS PROVIDED BY BYPASS STAGE AND CURRENT STEERING
Low noise amplifiers (LNAs) are disclosed herein. In certain embodiments, an LNA includes an input balun configured to convert a single-ended radio frequency (RF) receive signal to a differential RF receive signal, an amplifier chain configured to amplify the differential RF receive signal to generate a differential amplified RF receive signal, and an output balun configured to convert the differential amplified RF receive signal into a single-ended amplified RF receive signal. The LNA's amplifier chain is operable in multiple gain modes, and includes a first differential amplification stage, a second differential amplification stage, and a third differential amplification stage.
AMPLIFIER CIRCUIT HAVING ADJUSTABLE GAIN
An amplifier circuit having an adjustable gain is provided. The amplifier circuit includes an input terminal, an output terminal, an amplifier, and an attenuation circuit. The input terminal receives an input signal, which is in turn received by an input terminal of the amplifier. An output terminal of the amplifier outputs the input signal that is amplified. The attenuation circuit is coupled between the output terminal of the amplifier and the output terminal to provide a plurality of attenuation to the input signal that is amplified and generate a first attenuation signal, or between the input terminal and the output terminal to provide the plurality of attenuations to the input signal and generate a second attenuation signal. A difference between an impedance value of the input terminal of the attenuation circuit and an impedance value of the output terminal of the attenuation circuit is within a predetermined range.
BROADBAND LOW NOISE AMPLIFIER USING MULTIPLE CASCODE STAGES
Aspects of the disclosure include a wireless device comprising a module input to receive an input signal, a module output to provide an amplified output signal, a low-noise amplifier including an input amplification stage coupled to the input, and a plurality of output amplification stages switchably coupled to the input amplification stage, and a plurality of impedance-matching circuits, each impedance-matching circuit of the plurality of impedance-matching circuits having an input coupled to a respective output amplification stage and an output coupled to the module output.
Amplifier gain-tuning circuits and methods
Circuits and methods for improving the noise figure (NF) of an amplifier, particularly an LNA, in high-gain modes while improving the IIP3 of the amplifier in low-gain modes. The source of an amplifier common-source FET is coupled to circuit ground thorough a degeneration circuit comprising a two-port inductor and a bypass switch coupled in parallel with the inductor. A switched feedback circuit is coupled between the gate of the common-source FET and a feedback node in the amplifier output signal path. During a low gain mode, the inductor is entirely bypassed and the enabled feedback circuit lowers the input impedance of the common-source FET and reduces the gain of the amplifier circuit, essentially eliminating the need for a degeneration inductor. During a high gain mode, the source of the common-source FET is coupled to circuit ground through the inductor and the feedback circuit is disabled. Other gain modes are supported.
APPARATUS FOR OPTIMIZED TURN-OFF OF A CASCODE AMPLIFIER
An apparatus for turning off a cascode amplifier having a common-gate transistor and a common-source transistor is disclosed that includes the cascode amplifier, a feedback circuit, and a bias circuit. The feedback circuit is configured to receive a drain-voltage from the drain of the common-source transistor when the common-source transistor is switched to a first OFF state and produce a first feedback signal. The drain-voltage is equal to a source voltage of the common-gate transistor and the drain-voltage increases in response to switching the common-source transistor to the first OFF state. The bias circuit is configured to receive the first feedback signal and produce a bias-voltage. A first gate-voltage is produced from the bias-voltage. The cascode amplifier is configured to receive the first gate-voltage and a second gate-voltage. The common-gate transistor is configured to switch to a second OFF state in response to receiving the second gate-voltage.