H03F1/223

DC COUPLED AMPLIFIER HAVING PRE-DRIVER AND BIAS CONTROL
20230092922 · 2023-03-23 ·

A dc coupled amplifier includes a pre-driver, and amplifier and a bias control circuit. The pre-driver is configured to receive one or more input signals and amplify the one or more input signals to create one or more pre-amplified signals. The amplifier has cascode configured transistors configured to receive and amplify the one or more pre-amplified signals to create one or more amplified signals, the amplifier further having an output driver termination element. The bias control circuit is connected between the pre-driver and the amplifier, the bias control circuit receiving at least one bias current from the output driver termination element of the amplifier, wherein the pre-driver, the amplifier and the bias control circuit are all formed on a same die.

Bias Compensation Circuit of Amplifier
20220350359 · 2022-11-03 · ·

The present invention discloses a bias compensation circuit. The bias compensation circuit includes a detecting circuit, including a diode-connected transistor circuit, with a first end for receiving a first current, and a second end coupled to a first reference voltage end; and a first diode circuit, with a first end for receiving a second current, and a second end coupled to the first reference voltage end; wherein the detecting circuit provides a first voltage level according to the diode-connected transistor circuit, and provides a second voltage level according to the first diode circuit; a voltage-current converting circuit, coupled to the detecting circuit, for generating a first reference current according to the first voltage level and the second voltage level; and a bias circuit, coupled to the voltage-current converting circuit, for receiving the first reference current, to provide a bias voltage level according to the first reference current.

AMPLIFIERS WITH ATTENUATOR IN FEEDBACK AND BYPASS PATHS
20230090460 · 2023-03-23 ·

Methods and devices to support multiple gain states in amplifiers are described. The methods and devices are based on implementing a feedback element in the amplifier and adjusting the impedance of the feedback element to provide a desired gain while maintaining the overall performance of the amplifier and reducing degradation of the S12 parameter. The feedback element includes an adjustable attenuator and a tunable resistive element. The adjustable attenuator is provided in a path that is common to the feedback path and the bypass path of the amplifier. Exemplary implementations of adjustable attenuators are also presented.

Programmable optimized band switching LNA
11611319 · 2023-03-21 · ·

A front end module (FEM) integrated circuit (IC) architecture that uses the same LNA in each of several frequency bands extending over a wide frequency range. In some embodiments, switched impedance circuits distributed throughout the front end circuit allow selection of the frequency response and impedances that are optimized for particular performance parameters targeted for a desired device characteristic. Such switched impedance circuits tune the output and input impedance match and adjust the gain of the LNA for specific operating frequencies and gain targets. In addition, adjustments to the bias of the LNA can be used to optimize performance trade-offs between the total direct current (DC) power dissipated versus radio frequency (RF) performance. By selecting appropriate impedances throughout the circuit using switched impedance circuits, the LNA can be selectively tuned to operate optimally at a selected bias for operation within selected frequency bands.

Transfer printing for RF applications

A semiconductor structure for RF applications comprises: a first μTP GaN transistor on an SOI wafer or die; and a first resistor connected to the gate of said first transistor.

CONFIGURABLE PHASE TUNED MULTI-GAIN LNA ARCHITECTURE
20220345089 · 2022-10-27 ·

Methods and systems for a multi gain LNA architecture achieving minimum phase discontinuity between all the different active and passive gain modes that uses different LNA configurations and settings for single and multi-stage LNAs by a configurable combined output matching and phase adjusting circuitry.

POWER LIMITING SYSTEM AND METHOD FOR A LOW NOISE AMPLIFIER OF A FRONT END INTERFACE OF A RADIO FREQUENCY COMMUNICATION DEVICE
20220345098 · 2022-10-27 ·

A power limiting system and method for a low noise amplifier of a front end interface of a radio frequency communication device. A voltage regulator provides a source voltage to the low noise amplifier having a nominal voltage level that optimizes linearity of the low noise amplifier while a power level of a radio frequency input signal provided to an input of the low noise amplifier does not exceed a predetermined power level threshold. Detection circuitry detects when the power level of a radio frequency input signal exceeds the predetermined power level threshold and provides an adjust signal indicative thereof to the voltage regulator to reduce the source voltage below the nominal voltage level.

Standby Voltage Condition for Fast RF Amplifier Bias Recovery
20230081055 · 2023-03-16 ·

Various methods and circuital arrangements for biasing one or more gates of stacked transistors of an amplifier are possible where the amplifier is configured to operate in at least an active mode and a standby mode. Circuital arrangements can reduce bias circuit standby current during operation in the standby mode while allowing a quick recovery to normal operating conditions of the amplifier. Biasing an input transistor of the stacked transistors can be obtained by using a replica stack circuit.

Body tie optimization for stacked transistor amplifier

A transistor stack can include a combination of floating and body tied devices. Improved performance of the RF amplifier can be obtained by using a single body tied device as the input transistor of the stack, or as the output transistor of the stack, while other transistors of the stack are floating transistors. Transient response of the RF amplifier can be improved by using all body tied devices in the stack.

Data output device

A data output device is provided. The data output device includes a converter circuit configured to generate a conversion signal based on an output signal; a boosting circuit configured to generate a boosting signal based on the output signal; and an output circuit configured to generate the output signal based on an input signal and a feedback signal, the feedback signal being based on the conversion signal and the boosting signal.