Bias circuits and methods for silicon-based amplifier architectures that are tolerant of supply and bias voltage variations, bias current variations, and transistor stack height, and compensate for poor output resistance characteristics. Embodiments include power amplifiers and low-noise amplifiers that utilize a cascode reference circuit to bias the final stages of a cascode amplifier under the control of a closed loop bias control circuit. The closed loop bias control circuit ensures that the current in the cascode reference circuit is approximately equal to a selected multiple of a known current value by adjusting the gate bias voltage to the final stage of the cascode amplifier. The final current through the cascode amplifier is a multiple of the current in the cascode reference circuit, based on a device scaling factor representing the relative sizes of the transistor devices in the cascode amplifier and in the cascode reference circuit.

An amplification circuit includes: a power supply terminal that is connected to a power supply; a first transistor that has a first source terminal, a first drain terminal, and a first gate terminal to which a high-frequency signal is inputted; a second transistor that has a second source terminal that is connected to the first drain terminal, a second drain terminal that outputs a high frequency signal, and a second gate terminal that is grounded; a capacitor that is serially arranged on a second path that connects the second gate terminal and the power supply terminal; and a switch that is serially arranged on a first path, which connects the second drain terminal and the power supply terminal, or the second path. The second drain terminal and the second gate terminal are connected to each other via the switch and the capacitor.

An operational amplifier includes a single-stage amplifier and a current controller. The single-stage amplifier receives an input signal, and amplifies the input signal to generate an output signal, wherein the single-stage amplifier includes a voltage controlled current source circuit that operates in response to a bias voltage input. The current controller receives the input signal, and generates the bias voltage input according to the input signal. The bias voltage input includes a first bias voltage, a second bias voltage, a third bias voltage, and a fourth bias voltage. None of the first bias voltage, the second bias voltage, the third bias voltage, and the fourth bias voltage is directly set by the input signal of the single-stage amplifier.

An electronic device may include wireless circuitry with a baseband processor, a transceiver circuit, a front-end module, and an antenna. The front-end module may include amplifier circuitry such as a low noise amplifier for amplifying received radio-frequency signals. The amplifier circuitry is operable in a non-carrier-aggregation mode and a carrier aggregation mode. The amplifier circuitry may include an input transformer that is coupled to multiple amplifier stages such as a common gate amplifier stage, a cascode amplifier stage, and a common source amplifier stage. The common gate amplifier stage may include switches for selectively activating a set of cross-coupled capacitors to help maintain input impedance matching in the non-carrier-aggregation mode and the carrier-aggregation mode. The common source amplifier stage may include additional switches for activating and deactivating the common source amplifier stage to help maintain the gain in the non-carrier-aggregation mode and the carrier-aggregation mode.

Low noise amplifiers (LNAs) with low noise figure are provided. In certain embodiments, an LNA includes a single-ended LNA stage including an input for receiving a single-ended input signal from an antenna and an output for providing a single-ended amplified signal, a balun for converting the single-ended amplified signal to a differential signal, and a variable gain differential amplification stage for amplifying the differential signal from the balun. Implementing the LNA in this manner provides low noise figure, high gain, flexibility in controlling gain, and less sensitivity to ground/supply impedance.

Power amplifiers having improved gate oxide integrity are disclosed. In particular, a dynamic asymmetric cascode bias circuit is used to provide a bias signal to a cascode power amplifier stage. The bias signal swings in synchronicity with an output signal from the power amplifier stage. By having this dynamic bias signal, the gate-drain stress on the device is reduced, preserving gate oxide integrity. Preserving gate oxide integrity helps preserve the operational profile and extend device life, providing an enhanced user experience.

A power amplifier system is disclosed having an N number of transistors coupled together drain-to-source between a supply node and a fixed voltage node, wherein a first one of the N number of transistors coupled nearest to the fixed voltage node is configured to operate as an amplifying device in an ON-mode, and remaining ones of the N number of transistors are configured to operate as cascode devices in the ON-mode and to operate as turned-off switches in an OFF-mode. A controller is configured to place the N number of transistors in the first mode when a radio frequency (RF) signal is to be amplified by the first one of the N number of transistors and to place the N number of transistors in the second mode when the RF signal is not to be amplified by the first one of the N number of transistors.

An amplifier circuit includes an amplifier for generating an amplified input signal according to an input signal, and an attenuator circuit coupled to the amplifier. The attenuator circuit includes an input terminal for receiving the input signal or the amplified input signal, an output terminal, a reference voltage terminal, a zeroth resistor-switch circuit, a first resistor-switch circuit, and a second resistor-switch circuit. The zeroth resistor-switch circuit includes a first terminal coupled to the input terminal, a second terminal coupled to the output terminal, a zeroth switch coupled to the first terminal of the zeroth resistor-switch circuit and the second terminal of the zeroth resistor-switch circuit, a zeroth resistor coupled between the first terminal of the zeroth resistor-switch circuit and the second terminal of the zeroth resistor-switch circuit, a first resistor coupled between the zeroth resistor and the second terminal of the zeroth resistor-switch circuit, and a first switch.

Disclosed is an amplifying circuit and method. In one embodiment, an amplifying circuit, includes: a common-gate (CG) amplifier, wherein the CG amplifier comprises a first transistor, wherein source terminal and body terminal of the first transistor is coupled together through a first resistor.

When a current-to-voltage converter is used at low temperatures, the frequency band of measurable small currents is limited. Stray capacitance of a coaxial cable that takes out an output voltage of the current-to-voltage converter from inside to outside a cooling device narrows the operating frequency band of the current-to-voltage converter. The current-to-voltage converter of the present disclosure uses elements exclusively optimized for low-temperature operation (e.g., HEMTs) as electronic elements for current-to-voltage conversion. This configuration realizes current-to-voltage conversion characteristics with significantly more excellent sensitivity than that of the conventional technique even when the current-to-voltage converter is operated at a low temperature of 150 K or less or in cryogenic temperature conditions close to absolute zero. Further, a source follower circuit is added to an output stage of the current-to-voltage conversion circuit to isolate the effect of stray capacitance added to the output side of the current-to-voltage conversion circuit and achieve a wider bandwidth.