A fully differential power amplifier has an input matching network, a plurality of stacked transistors connected by a plurality of inter stack networks (ISNs), and an output matching network for amplification and conditioning of signal components. The differential amplifier uses a modified cascode FET topology with the FETs connected by gate decoupling capacitors to strongly attenuate common mode oscillations and eliminate the need for a source degeneration inductor or matching transformer. Inter stack networks provide signal conditioning and filtering between amplification stages to improve amplifier performance metrics such as long-term reliability, output power, and efficiency.

An amplifier circuit amplifies a radio-frequency signal. The amplifier circuit includes an amplifier, an input matching circuit connected to an input side of the amplifier and matches impedance, and a protection circuit connected to a node in a path within a path between an input matching circuit and the amplifier. The protection circuit includes a first diode connected between the node and a ground, and a second diode connected in parallel with the first diode and connected in a direction opposite to the first diode between the node and the ground. A threshold voltage of each of the first diode and the second diode is greater than a maximum voltage amplitude of the input signal at the node and is less than a difference between a withstand voltage of the amplifier and the bias voltage.

An active biconical antenna and a receive array comprising a combination of active biconical and Vivaldi antennas. In one configuration, the active biconical antenna includes upper and lower cones. Each cone has a respective truncated apex. First and second feed points are respectively connected to the truncated apexes of the upper and lower cones and to first and second conductors. The active biconical antenna further includes a buffer amplifier having respective input terminals connected to the first and second conductors. The buffer amplifier has an input impedance that is impedance matched to an antenna impedance at and above but not below a frequency f.sub.c and is higher than the antenna impedance at frequencies substantially less than f.sub.c. The buffer amplifier also has an output impedance that is impedance matched to a system impedance at frequencies both above and below f.sub.c. A length of the first and second conductors is less than a wavelength at the frequency f.sub.c.

Methods and circuital arrangements for turning OFF branches of a multi-branch cascode amplifier are presented. First and second switching arrangements coupled to a branch allow turning OFF the branch while protecting transistors of the branch from a supply voltage that may be greater than a tolerable voltage of the transistors. The first switching arrangement includes a transistor-based switch that is in series connection with the transistors of the branch. The first switching arrangement drops the supply voltage during the OFF state of the branch and provides a conduction path for a current through the branch during the ON state of the branch. A resistor and a shunting switch are coupled to a gate of the transistor-based switch to reduce parasitic coupling effects of the transistor-based switch upon an RF signal coupled to the branch during the ON state and OFF state of the branch.

A system and method which includes receiving an input signal and providing, by an amplifier circuit, an output signal in response to the input signal, the output signal having an envelope. An envelope detection signal corresponding to the envelope of the output signal is generated. A bias current provided to an amplifier circuit is adjusted based upon the envelope detection signal. The amplifier circuit includes an amplifier and a transformer, the transformer being configured to establish a magnetically coupled feedback loop from an output of the amplifier to an input of the amplifier.

A receiver front end having low noise amplifiers (LNAs) is disclosed herein. A cascode having a “common source” configured input FET and a “common gate” configured output FET can be turned on or off using the gate of the output FET. A first switch is provided that allows a connection to be either established or broken between the source terminal of the input FET of each LNA. A drain switch is provided between the drain terminals of input FETs to place the input FETs in parallel. This increases the g.sub.m of the input stage of the amplifier, thus improving the noise figure of the amplifier.

A dual-band low-noise amplifier circuit includes an amplification sub-circuit and a switch frequency selection circuit; the amplification sub-circuit is used for performing gain amplification on a radio frequency signal to be amplified to obtain an amplified radio frequency signal, and outputting the amplified radio frequency signal; the switch frequency selection circuit is connected to the amplification sub-circuit, and is used for controlling the state of a switch in the switch frequency selection circuit on the basis of a target frequency band corresponding to the radio frequency signal to be amplified, so that the dual-band low-noise amplifier circuit meets optimal performance in the target frequency band. In this way, low-noise amplification of dual-band signals is achieved by means of the reconfigurable structure of the low-noise amplifier circuit, and parameters such as noise figure, gain, and linearity can be kept in optimal states in each frequency band.

A phase compensation circuit module includes at least a variable resistor, a detection component and a control component. The detection component has a detection end connected with a signal input end of a power amplifier, and is configured to detect an input signal of the signal input end. The control component is connected with the detection component, and is configured to output a control signal according to the input signal detected by the detection component. The variable resistor is connected with an output end of the control component, and is configured to change resistance linked to the power amplifier according to the control signal, the variable resistor constitutes a loop of the power amplifier and is configured to form on-resistance of a transistor of the power amplifier. The on-resistance of the transistor is configured to change as a phase of an output signal of the power amplifier changes.

An active biconical antenna and a receive array comprising a combination of active biconical and Vivaldi antennas. In one configuration, the active biconical antenna includes upper and lower cones. Each cone has a respective truncated apex. First and second feed points are respectively connected to the truncated apexes of the upper and lower cones and to first and second conductors. The active biconical antenna further includes a buffer amplifier having respective input terminals connected to the first and second conductors. The buffer amplifier has an input impedance that is impedance matched to an antenna impedance at and above but not below a frequency f.sub.c and is higher than the antenna impedance at frequencies substantially less than f.sub.c. The buffer amplifier also has an output impedance that is impedance matched to a system impedance at frequencies both above and below f.sub.c. A length of the first and second conductors is less than a wavelength at the frequency f.sub.c.

Various aspects of integrated amplifiers, layouts for the integrated amplifiers, and packaged arrangements of the amplifiers are described. In one example, an amplifier includes an amplifier cell, and a biasing network coupled to the common gate transistor in the amplifier cell. The amplifier cell includes a common source transistor and a common gate transistor in a cascode arrangement, where at least one of the common source transistor and the common gate transistor comprises a field plate. Among other advantages, the amplifiers described herein can be biased with relatively high voltages and still operate like a single a common source transistor, without sacrificing reliability, performance, or requiring additional off-chip components, such as biasing networks of resistors and inductors.