A transmitter is configured to generate a DOCSIS signal for transmission onto a frequency-selective coaxial cable. The transmitter comprises a first reverse tilt filter circuit, a digital predistortion circuit, a forward tilt filter, a wideband equalizer, a second reverse tilt filter, and a power amplifier. The responses of the tilt filters may be set based on the frequency response of the frequency-selective coaxial cable to which the transmitter is intended to be coupled. The predistortion circuit may compensate for distortion introduced by circuitry of the transmitter. The equalizer circuit may be operable to compensate for undesired linear response of other circuitry of the transmitter.

A method for communication includes producing an error signal by comparing a driving signal applied to a transmitter to an output signal generated by the transmitter in response to the driving signal. The error signal is decomposed into a linear component having a first memory depth and a nonlinear component having one or more polynomial orders and a second memory depth that is less than the first memory depth. First coefficients, up to the first memory depth, of a linear predistortion kernel are computed for application to the driving signal so as to compensate for the linear component of the error signal. Second coefficients for the one or more polynomial orders, up to the second memory depth, of a nonlinear predistortion kernel are computed so as to compensate for the nonlinear component of the error signal. Operation of the transmitter is optimized using the first and second coefficients.

A method for communication includes producing an error signal by comparing a driving signal applied to a transmitter to an output signal generated by the transmitter in response to the driving signal. The error signal is decomposed into a linear component having a first memory depth and a nonlinear component having one or more polynomial orders and a second memory depth that is less than the first memory depth. First coefficients, up to the first memory depth, of a linear predistortion kernel are computed for application to the driving signal so as to compensate for the linear component of the error signal. Second coefficients for the one or more polynomial orders, up to the second memory depth, of a nonlinear predistortion kernel are computed so as to compensate for the nonlinear component of the error signal. Operation of the transmitter is optimized using the first and second coefficients.

The embodiments described herein include amplifiers that are typically used in radio frequency (RF) applications. Specifically, the amplifiers described herein include a phase distortion compensation circuit that can compensate for input impedance variations that could otherwise lead to reduced efficiency and power performance. In one specific embodiment, the phase distortion compensation circuit is used to compensate for input impedance variations in the peaking amplifiers of a Doherty amplifier. In such embodiments, the phase distortion compensation circuit can absorb the non-linear input impedances of the peaking amplifiers in a way that may facilitate improved phase maintenance between the carrier and peaking stages of the Doherty amplifier.

A radio frequency (RF) amplifier circuit includes a field effect transistor (FET) (e.g., a FET belonging to a III-V FET enhancement group), where the FET includes a gate terminal coupled to an RF input node. The circuit further includes a prematch and biasing network coupled between a bias voltage node and the RF input node. The prematch and biasing network includes a nonlinear gate current blocking device configured to block a current from flowing between the bias voltage node and the RF input node.

A structure having: a plurality of field effect transistors (FETs) connected between a common input and a common output, each one of the field effect transistors comprises: a source region, a drain region, and a gate electrode for controlling carriers through a channel region of a transistor region of the structure between the source region and the drain region; a plurality of diodes, each one of the diodes being associated with a corresponding one of the plurality of FETs, each one of the diodes having an electrode in Schottky contact with a diode region of the corresponding one of the FETs. The gate electrode and the diode electrode extend along parallel lines. The source region, the drain region, the channel region, and a diode region having therein the diode are disposed along a common line.

An transmitter arrangement and a method therein are provided for linearization of an active antenna array. The active antenna array comprises a plurality of antenna elements, which are associated with a plurality of power amplifiers. The active antenna array is further associated with a precoder having a number of input and output ports. The method comprises obtaining a first signal provided to the antenna array via a first input port of the precoder. The method further comprises adapting a pre-distorting linearizer connected to the first input port based on the first signal and on feedback from the plurality of antenna elements, resulting from the propagation of the first signal via the precoder, and via the plurality of power amplifiers. Embodiments are also provided for adapting a pre-distorting linearizer based on a plurality of input signals and feedback from the plurality of antenna elements.

A predistorter has a first capacitor, a first bias input circuit, a second bias input circuit, a second capacitor and an impedance conversion circuit. A first end of the first capacitor is coupled to a first node of the amplifier. The impedance conversion circuit has a first resistor and a field-effect transistor (FET) and is used to perform an impedance conversion to provide a variable capacitance. A gate of the FET is coupled to an output end of the first bias input circuit, one of a source and a drain of the FET is coupled to a second end of the first capacitor and a first end of the first resistor, and another of the source and the drain of the FET is coupled to an output end of the second bias input circuit, first end of the second capacitor and a second end of the first resistor.

The invention relates to an electrical circuit (1) for transmitting a useful analogue signal which has a signal transmission path (16) with an input path (2) and an output path (3) and one or more switches (4-6), with which switch or switches the useful signal which is carried on the input path (2) can be connected through to the output path (3) by the switch or the switches (4-6) being switched to the switched-on state. According to the invention, the electrical circuit (1) comprises a compensation circuit (7) which has one or more auxiliary switches (17) of the same type as the switch or the switches (4-6), and the auxiliary switch or switches (17) is or are coupled to the signal transmission path (16) such that said auxiliary switch or switches generates or generate signal distortion in the switched-on state, which signal distortion substantially compensates for a distortion in the useful analogue signal which is generated by the switch or switches (4-6).

The invention relates to an electrical circuit (1) for transmitting a useful analogue signal which has a signal transmission path (16) with an input path (2) and an output path (3) and one or more switches (4-6), with which switch or switches the useful signal which is carried on the input path (2) can be connected through to the output path (3) by the switch or the switches (4-6) being switched to the switched-on state. According to the invention, the electrical circuit (1) comprises a compensation circuit (7) which has one or more auxiliary switches (17) of the same type as the switch or the switches (4-6), and the auxiliary switch or switches (17) is or are coupled to the signal transmission path (16) such that said auxiliary switch or switches generates or generate signal distortion in the switched-on state, which signal distortion substantially compensates for a distortion in the useful analogue signal which is generated by the switch or switches (4-6).