Systems and methods related to power amplification and power supply control. A power amplification control system can include an interface configured to receive a transceiver control signal from a transceiver. The power amplification control system can include a power amplifier control component configured to generate a power amplifier control signal based on the transceiver control signal from the transceiver and a power supply control component configured to generate a power supply control signal based on the transceiver control signal from the transceiver and to generate the power supply control signal based on a local control signal from the power amplifier control component.

Systems and methods related to power amplification and power supply control. A power amplification control system can include an interface configured to receive a transceiver control signal from a transceiver. The power amplification control system can include a power amplifier control component configured to generate a power amplifier control signal based on the transceiver control signal from the transceiver and a power supply control component configured to generate a power supply control signal based on the transceiver control signal from the transceiver and to generate the power supply control signal based on a local control signal from the power amplifier control component.

Disclosed is an electronic device including a power amplifier (PA) configured to amplify a transmission signal, a matching circuit configured to be connected with the PA and to form a load impedance, a filter configured to be connected with the matching circuit, and a control circuit configured to control a state of at least one of a bias of the PA, the matching circuit, and the filter. The control circuit may identify a network to which the electronic device is connected among a first network and a second network and may operate the matching circuit in one of a first state, a second state, and a third state based on the identified network.

An amplifier includes a Field Effect Transistor (FET) or a Bipolar Junction Transistor (BJT) with “hard saturation.”; where the FET or the BJT to has a nearly constant drain or collector current when the drain or collector voltage is greater than the pinchoff voltage. The amplifier further includes a bias network, configured to provide a DC voltage to the FET or the BJT, a means for isolating the DC voltage from the matching network, an electrical load, and a matching network which transforms the electrical load to a resistance between the drain and the source or the collector and emitter which causes the drain or collector voltage to be greater than the pinchoff voltage over the entire cycle of the sinusoidal voltage applied to the gate, whereby the amplifier is linear.

Circuits and devices related to radio-frequency amplifiers. In some embodiments, a radio-frequency amplifier can include a plurality of narrow band power amplifiers. Each narrow band power amplifier can be configured to operate with a high voltage in an average power tracking mode and be capable of being coupled to an output filter associated with a respective individual frequency band. Each narrow band power amplifier can be sized smaller than a wide band power amplifier configured to operate with more than one of the frequency bands associated with the plurality of narrow band power amplifiers.

Circuits and devices related to radio-frequency amplifiers. In some embodiments, a radio-frequency amplifier can include a plurality of narrow band power amplifiers. Each narrow band power amplifier can be configured to operate with a high voltage in an average power tracking mode and be capable of being coupled to an output filter associated with a respective individual frequency band. Each narrow band power amplifier can be sized smaller than a wide band power amplifier configured to operate with more than one of the frequency bands associated with the plurality of narrow band power amplifiers.

A power amplifier circuit includes an amplifier that receives an input signal with an alternating current and outputs an output signal obtained by amplifying power of the input signal to a first node; an inductive element that is connected between the first node and a second node; and a variable capacitor that is connected between the second node and a reference potential, and whose electrostatic capacitance increases as power of the output signal increases.

Power amplifier apparatuses and techniques for optimizing the design of power amplifiers are disclosed. In one aspect, a method for optimizing a power amplifier includes selecting a circuit topology for the power amplifier. The circuit topology includes one or more photoconductive switches and an impedance matching network including one or more parameter values representative of the impedance matching network or the photoconductive switches that can be adjusted. The method further includes selecting one or more optimization goals for the impedance matching network and the one or more photoconductive switches, and adjusting the one or more parameter values according to the one or more optimization goals. The one or more optimization goals include an efficiency at a particular power output.

A circuit includes a first system-on-chip (SoC) driven by a first clock generator and a second SoC driven by a second clock generator where the first clock generator and the second clock generator have independent time bases. The first and second clock generators are synchronized using an RLC circuit external to the first clock generator and the second clock generator that converts an output of the first clock generator into current pulses and injects the current pulses into the second clock generator to pull an output of the second clock generator into synchronization with the output of the first clock generator. The RLC circuit converts a voltage output of the first clock generator into current pulses at the resonant frequency or specific harmonics of the output of the first clock generator. The second clock generator may include a ring oscillator into which the current pulses are injected.

A circuit includes a first system-on-chip (SoC) driven by a first clock generator and a second SoC driven by a second clock generator where the first clock generator and the second clock generator have independent time bases. The first and second clock generators are synchronized using an RLC circuit external to the first clock generator and the second clock generator that converts an output of the first clock generator into current pulses and injects the current pulses into the second clock generator to pull an output of the second clock generator into synchronization with the output of the first clock generator. The RLC circuit converts a voltage output of the first clock generator into current pulses at the resonant frequency or specific harmonics of the output of the first clock generator. The second clock generator may include a ring oscillator into which the current pulses are injected.