A dual operation mode power amplifier is disclosed. In the power amplifier in accordance with an embodiment of the present invention, a bias circuit part can be converted to decrease power consumption. Different from the prior art, performance of the present invention is not reduced in a high power mode, and no additional passive components like inductors or transformers with a large area are necessary to be further added. Furthermore, a tunable impedance matching circuit provides impedances respectively matching impedances of a fully differential amplifier and a single-ended amplifier, thereby improving the performance of the power amplifier.

An exemplary multipath feedforward amplifier includes a plurality of amplification stages configured to form at least partially distinct amplification paths extending from an input terminal to an output terminal, each amplification path defined by a respective subset of the plurality of amplification stages, wherein at least one amplification stage is a band pass resonator. In various implementations, multipath feedforward amplifier can maximize gain at a frequency of interest by having an amplification path that cascades band pass resonators. In various implementations, the plurality of amplification paths are configured to optimize gain at a center frequency ranging from about 2 GHz to about 3 GHz.

Apparatus and methods for multi-mode low noise amplifiers (LNAs) are provided herein. In certain configurations, a radio frequency (RF) system includes a multi-mode LNA including at least a first amplification stage and a second amplification stage electrically connected in a cascade. The RF system further includes a mode control circuit, which receives a mode selection signal and controls the biasing of the first and second amplification stages based on the mode selection signal. The mode control circuit operates the multi-mode LNA in one of a plurality of modes including both a first mode in which the LNA operates with higher gain and better noise figure and a second mode in which the LNA operates with lower gain and higher linearity. Controlling the mode of the multi-mode LNA using the mode selection signal allows the multi-mode LNA to advantageously achieve both the benefits of low noise figure and high linearity.

Apparatus and methods for multi-mode low noise amplifiers (LNAs) are provided herein. In certain configurations, a radio frequency (RF) system includes a multi-mode LNA including at least a first amplification stage and a second amplification stage electrically connected in a cascade. The RF system further includes a mode control circuit, which receives a mode selection signal and controls the biasing of the first and second amplification stages based on the mode selection signal. The mode control circuit operates the multi-mode LNA in one of a plurality of modes including both a first mode in which the LNA operates with higher gain and better noise figure and a second mode in which the LNA operates with lower gain and higher linearity. Controlling the mode of the multi-mode LNA using the mode selection signal allows the multi-mode LNA to advantageously achieve both the benefits of low noise figure and high linearity.

Provided is a power amplification module that includes: a first amplification circuit that amplifies a first signal and outputs the amplified first signal as a second signal; a second amplification circuit that amplifies the second signal and outputs the amplified second signal as a third signal; and a feedback circuit that re-inputs/feeds back the second signal outputted from the first amplification circuit to the first amplification circuit as the first signal. The operation of the first amplification circuit is halted and the first signal passes through the feedback circuit and is outputted as the second signal at the time of a low power output mode.

Provided is a power amplification module that includes: a first amplification circuit that amplifies a first signal and outputs the amplified first signal as a second signal; a second amplification circuit that amplifies the second signal and outputs the amplified second signal as a third signal; and a feedback circuit that re-inputs/feeds back the second signal outputted from the first amplification circuit to the first amplification circuit as the first signal. The operation of the first amplification circuit is halted and the first signal passes through the feedback circuit and is outputted as the second signal at the time of a low power output mode.

Methods and structures for improving the performance of integrated semiconductor transistors operating at high frequency and/or high power are described. Two capacitors may be connected to an input of a semiconductor transistor and tuned to suppress second-harmonic generation and to transform and match the input impedance of the device. A two-stage tuning procedure is described. The transistor may comprise gallium nitride and may be configured as a power transistor capable of handling up to 1000 W of power. A tuned transistor may operate at frequencies up to 6 GHz with a peak drain efficiency greater than 60%.

Methods and structures for improving the performance of integrated semiconductor transistors operating at high frequency and/or high power are described. Two capacitors may be connected to an input of a semiconductor transistor and tuned to suppress second-harmonic generation and to transform and match the input impedance of the device. A two-stage tuning procedure is described. The transistor may comprise gallium nitride and may be configured as a power transistor capable of handling up to 1000 W of power. A tuned transistor may operate at frequencies up to 6 GHz with a peak drain efficiency greater than 60%.

Methods and structures for improving the performance of integrated semiconductor transistors operating at high frequency and/or high power are described. Two capacitors may be connected to an input of a semiconductor transistor and tuned to suppress second-harmonic generation and to transform and match the input impedance of the device. A two-stage tuning procedure is described. The transistor may comprise gallium nitride and may be configured as a power transistor capable of handling up to 1000 W of power. A tuned transistor may operate at frequencies up to 6 GHz with a peak drain efficiency greater than 60%.

Methods and structures for improving the performance of integrated semiconductor transistors operating at high frequency and/or high power are described. Two capacitors may be connected to an input of a semiconductor transistor and tuned to suppress second-harmonic generation and to transform and match the input impedance of the device. A two-stage tuning procedure is described. The transistor may comprise gallium nitride and may be configured as a power transistor capable of handling up to 1000 W of power. A tuned transistor may operate at frequencies up to 6 GHz with a peak drain efficiency greater than 60%.