A variable gain amplifier (VGA) is provided. The VGA includes at least one amplifier circuit, at least one current-steering circuit and at least one bias voltage circuit. Each current-steering circuit is coupled to its corresponding amplifier circuit. Each bias voltage circuit is coupled to its corresponding current-steering circuit to provide a positive bias voltage to each current-steering circuit.

A multiple-stage amplifier includes a driver stage transistor characterized by a first power density, and a final stage transistor characterized by a second power density that is larger than the first power density. A first drain bias circuit is coupled to a first drain terminal of the driver stage transistor, and is configured to provide a first drain bias voltage to the first drain terminal. A second drain bias circuit is coupled to a second drain terminal of the final stage transistor, and is configured to provide a second drain bias voltage to the second drain terminal, where the second drain bias voltage equals the first drain bias voltage. An interstage impedance matching circuit is coupled between the first drain terminal and a gate terminal of the final stage transistor. The multiple-stage amplifier may be included in a Doherty power amplifier, a transceiver, and/or a transceiver array.

A multiple-stage amplifier includes a driver stage transistor characterized by a first power density, and a final stage transistor characterized by a second power density that is larger than the first power density. A first drain bias circuit is coupled to a first drain terminal of the driver stage transistor, and is configured to provide a first drain bias voltage to the first drain terminal. A second drain bias circuit is coupled to a second drain terminal of the final stage transistor, and is configured to provide a second drain bias voltage to the second drain terminal, where the second drain bias voltage equals the first drain bias voltage. An interstage impedance matching circuit is coupled between the first drain terminal and a gate terminal of the final stage transistor. The multiple-stage amplifier may be included in a Doherty power amplifier, a transceiver, and/or a transceiver array.

A power amplifier system having a power amplifier with a signal input and a signal output and bias circuitry is disclosed. The bias circuitry includes a bandgap reference circuit coupled between a reference node and a fixed voltage node. A bias generator has a bias input coupled to the reference node and a bias output coupled to the signal input. Also included is a first digital-to-analog converter having a first converter output coupled to the reference node, a first voltage input, and a first digital input, wherein the first digital-to-analog converter is configured to adjust a reference voltage at the reference node in response to a first digital setting received at the first digital input. The first digital setting correlates with an indication of temperature of the power amplifier.

An amplifier includes amplifier circuits connected in series between a ground and a power supply, each amplifier circuit includes: a transistor; and a first capacitance, one end of which is connected to a drain of the transistor, a first amplifier circuit connected closest to the power supply includes a load connected between the drain of the transistor and the power supply, each of the amplifier circuits except for the first amplifier circuit includes a load connected between the drain of the transistor of an own amplifier circuit and a source of the transistor of an amplifier circuit adjacent to the own amplifier circuit, each of the amplifier circuits except for an amplifier circuit connected farthest from the power supply includes a second capacitance connected between the source of the transistor and the ground, and the second capacitance has a capacitance value larger than a capacitance value of the first capacitance.

A radio frequency power amplifier circuit includes a controllable attenuation circuit, an input matching circuit, a drive amplification circuit, an inter-stage matching circuit, a power amplification circuit and an output matching circuit connected in sequence, and respectively configured to switch between a negative gain mode and a non-negative gain mode of the radio frequency power amplifier circuit based on a mode control signal, match the impedance between the controllable attenuation circuit and the drive amplification circuit, amplify a signal, configured to match the impedance between the drive amplification circuit and the power amplification circuit, amplify a signal, and match the impedance between the radio frequency power amplifier circuit and a post-stage circuit. A feedback circuit is connected across the drive amplification circuit, and is configured to adjust a gain.

A low noise amplifier that may include a first input port, a second input port, a first capacitor, a second capacitor, a first variable capacitor, a second variable capacitor, an inductor, a bias circuit, a tuning circuit, a first output circuit having a first output, a second output circuit having a second output; wherein the first input port is electrically coupled to a first end of the second variable capacitor, to a first end of the first capacitor, to an input of the first output circuit, and to a first port of the inductor; wherein the second input port is electrically coupled to a second end of the first variable capacitor, to a second end of the second capacitor, to an input of the second output circuit, and to a second port of the inductor; wherein a first port of the first varactor is electrically coupled to a second end of the first capacitor; wherein a second port of the second varactor is electrically coupled to a first end of the second capacitor; wherein the bias circuit is configured to supply a bias voltage to a third port of the inductor; and wherein the tuning circuit is configured to control a capacitance of the first varactor and a capacitance of the variable capacitor.

A low noise amplifier that may include a first input port, a second input port, a first capacitor, a second capacitor, a first variable capacitor, a second variable capacitor, an inductor, a bias circuit, a tuning circuit, a first output circuit having a first output, a second output circuit having a second output; wherein the first input port is electrically coupled to a first end of the second variable capacitor, to a first end of the first capacitor, to an input of the first output circuit, and to a first port of the inductor; wherein the second input port is electrically coupled to a second end of the first variable capacitor, to a second end of the second capacitor, to an input of the second output circuit, and to a second port of the inductor; wherein a first port of the first varactor is electrically coupled to a second end of the first capacitor; wherein a second port of the second varactor is electrically coupled to a first end of the second capacitor; wherein the bias circuit is configured to supply a bias voltage to a third port of the inductor; and wherein the tuning circuit is configured to control a capacitance of the first varactor and a capacitance of the variable capacitor.

A buffer circuit for a radio frequency (RF) signal includes a single leg and a feedback mesh. The single leg is coupled between a voltage supply and ground. The single leg includes a pMOS FET and an nMOS FET, and an output terminal defined at drain terminals of the pMOS FET and the nMOS FET. The buffer circuit includes an input terminal capacitively coupled to gates of the pMOS FET and the nMOS FET. The input terminal is configured to receive the RF signal, and a buffered signal is provided on the output terminal. The feedback mesh is coupled to the output terminal and coupled to the gates of the pMOS FET and the nMOS FET. The feedback mesh includes a series-coupled inductive-resistive feedback impedance, and a resistive feedback impedance in parallel with the series-coupled inductive-resistive feedback impedance.

A buffer circuit for a radio frequency (RF) signal includes a single leg and a feedback mesh. The single leg is coupled between a voltage supply and ground. The single leg includes a pMOS FET and an nMOS FET, and an output terminal defined at drain terminals of the pMOS FET and the nMOS FET. The buffer circuit includes an input terminal capacitively coupled to gates of the pMOS FET and the nMOS FET. The input terminal is configured to receive the RF signal, and a buffered signal is provided on the output terminal. The feedback mesh is coupled to the output terminal and coupled to the gates of the pMOS FET and the nMOS FET. The feedback mesh includes a series-coupled inductive-resistive feedback impedance, and a resistive feedback impedance in parallel with the series-coupled inductive-resistive feedback impedance.