Radio frequency amplifiers with overload protection are provided herein. In certain configurations, an RF amplifier system includes an RF amplifier that receives an RF signal from an input terminal and that generates an amplified RF signal at an output terminal, and an overload detection circuit that generates a detection signal indicating a detected signal level of the RF amplifier. The RF amplifier includes an amplification device that amplifies the RF signal and a degeneration circuit that provides degeneration to the amplification device. Additionally, the detection signal is operable to control an amount of degeneration provided by the degeneration circuit so as to protect the RF amplifier from overload.

Radio frequency amplifiers with overload protection are provided herein. In certain configurations, an RF amplifier system includes an RF amplifier that receives an RF signal from an input terminal and that generates an amplified RF signal at an output terminal, and an overload detection circuit that generates a detection signal indicating a detected signal level of the RF amplifier. The RF amplifier includes an amplification device that amplifies the RF signal and a degeneration circuit that provides degeneration to the amplification device. Additionally, the detection signal is operable to control an amount of degeneration provided by the degeneration circuit so as to protect the RF amplifier from overload.

Embodiments of the disclosure are drawn to apparatuses and methods for a tunable digital power amplifier (DPA). The tunable DPA may be coupled to a reconfigurable capacitor to form a frequency tunable DPA. The capacitance of the reconfigurable capacitor may be adjusted to optimize the DPA to operate at a desired frequency band. The single tunable DPA may operate over a wide range of frequencies.

A random access memory (RAM) including a deserializer is disclosed. The RAM further comprises a continuous-time linear equalizer (CTLE) including a first input terminal that receives an input signal for the RAM and a first output terminal communicatively connected to the deserializer, the CTLE configured to perform a channel gain compensation on the input signal received by the first input terminal and to transmit the compensated input signal to the deserializer. The RAM may further comprise a decision feedback equalizer (DFE) including a second input terminal communicatively connected to the CTLE and a second output terminal communicatively connected to the deserializer, the DFE configured to reduce an inter-symbol interference (ISI) of the input signal.

The disclosed technology is related to a radio-frequency (RF) amplifier having a bypass circuit and a resonant structure to improve performance in a bypass mode (e.g., a low gain mode). The disclosed amplifiers have a resonant structure that effectively isolates an amplifier core from a bypass circuit. For example, in a bypass mode, the resonant structure is configured to create an open impedance looking into the amplifier core input. This effectively removes any loading from the amplifier core to the bypass circuit. The disclosed amplifiers with resonant structures improve linearity performance in bypass modes due at least in part to the open impedance to the amplifier core provided by the resonant structure.

The disclosed technology is related to a radio-frequency (RF) amplifier having a bypass circuit and a resonant structure to improve performance in a bypass mode (e.g., a low gain mode). The disclosed amplifiers have a resonant structure that effectively isolates an amplifier core from a bypass circuit. For example, in a bypass mode, the resonant structure is configured to create an open impedance looking into the amplifier core input. This effectively removes any loading from the amplifier core to the bypass circuit. The disclosed amplifiers with resonant structures improve linearity performance in bypass modes due at least in part to the open impedance to the amplifier core provided by the resonant structure.

Embodiments of RF amplifiers and packaged RF amplifier devices each include a transistor with a drain-source capacitance that is relatively low, an output impedance matching circuit, and a harmonic termination circuit. The impedance matching circuit includes a harmonic termination circuit, which includes a first inductance (a first plurality of bondwires) and a first capacitance coupled in series between the transistor output and a ground reference node. An equivalent capacitance from a combination of the first inductive element and the first capacitance in series effectively increases the drain-source capacitance by at least 10 percent. The impedance matching circuit also includes a second inductance (a second plurality of bondwires) and a second capacitance coupled in series between the transistor output and the ground reference node, where the second inductance and the second capacitance are directly connected. The first and second capacitances may be metal-insulator-metal capacitors in an integrated passive device.

Embodiments of RF amplifiers and packaged RF amplifier devices each include a transistor with a drain-source capacitance that is relatively low, an output impedance matching circuit, and a harmonic termination circuit. The impedance matching circuit includes a harmonic termination circuit, which includes a first inductance (a first plurality of bondwires) and a first capacitance coupled in series between the transistor output and a ground reference node. An equivalent capacitance from a combination of the first inductive element and the first capacitance in series effectively increases the drain-source capacitance by at least 10 percent. The impedance matching circuit also includes a second inductance (a second plurality of bondwires) and a second capacitance coupled in series between the transistor output and the ground reference node, where the second inductance and the second capacitance are directly connected. The first and second capacitances may be metal-insulator-metal capacitors in an integrated passive device.

Power amplifiers, amplifier systems, and related methods are disclosed herein. In one example embodiment, the amplifier system includes a bias controller that enables fast switching between an on state bias voltage and an off state bias voltage for the power amplifier. The bias controller can transition a low impedance switch to an on state to electrically couple a first electrode of a charge holding capacitor to an input of the power amplifier. The charge holding capacitor can be pre charged with the on state bias voltage to quickly provide the on state bias voltage to the power amplifier. The bias controller can also transition the low impedance switch to an off state to couple the input of the power amplifier to the off state bias voltage.

The invention relates to high-frequency amplifier apparatuses suitable for generating power outputs of at least 1 kW at frequencies of at least 2 MHz. The apparatuses include two LDMOS transistors each connected by their source connection to ground. The transistors can have the same design and can be arranged in an assembly (package). The apparatus also includes a circuit board lying against a cooling plate, which can be connected to ground, and the assembly is arranged on or against the circuit board. The apparatuses have a power transformer, whose primary winding is connected to the drain connections of the transistors, and a signal transmitter. A secondary winding of the signal transmitter can be connected to the gate connections of the two transistors. Each of the gate connections can be connected to ground via at least one voltage-limiting structural element.