An RF receiver circuit configuration and design limited by conditions and frequencies to simultaneously provide steady state low-noise signal amplification, frequency down-conversion and image signal rejection. The invention provides combined circuits of an RF transceiver architecture that measure antenna reflected power relative to forward power using the error amplifier signal to adjust the gain of the variable gain amplifier in order to compensate for the mismatch between forward reflected power and forward power at the antenna in order to achieve constant radiated power. The RF receiver circuit may be implemented as one of a CMOS single chip device or as part of an integrated system of CMOS components.

Various examples are directed to a power amplifier circuit, comprising a digital predistortion circuit, first and second power amplifiers, and a bias feedback circuit. The digital predistortion circuit may be configured to generate a predistorted input signal based at least in part on an input signal. The first power amplifier may be configured to generate a first amplified signal based at least in part on the predistorted input signal. The second power amplifier may be configured to generate a second amplified signal based at least in part on the predistorted input signal. The bias feedback circuit may be configured to adjust at least one of a bias of the first power amplifier or a bias of the second power amplifier to align a first nonlinear behavior of the first power amplifier with a second nonlinear behavior of the second power amplifier.

Various examples are directed to a power amplifier circuit, comprising a digital predistortion circuit, first and second power amplifiers, and a bias feedback circuit. The digital predistortion circuit may be configured to generate a predistorted input signal based at least in part on an input signal. The first power amplifier may be configured to generate a first amplified signal based at least in part on the predistorted input signal. The second power amplifier may be configured to generate a second amplified signal based at least in part on the predistorted input signal. The bias feedback circuit may be configured to adjust at least one of a bias of the first power amplifier or a bias of the second power amplifier to align a first nonlinear behavior of the first power amplifier with a second nonlinear behavior of the second power amplifier.

An amplifier circuit configuration capable of processing non-contiguous intra-band carrier aggregate (CA) signals using amplifiers is disclosed herein. In some cases, each of a plurality of amplifiers is an amplifier configured as a cascode (i.e., a two-stage amplifier having two transistors, the first configured as a common source input transistor, e.g., input field effect transistor (FET), and the second configured in a common gate configuration as a cascode output transistor, (e.g. cascode output FET). In other embodiments, the amplifier may have additional transistors (i.e., more than two stages and/or stacked transistors). The amplifier circuit configuration can be operated in either single mode or split mode. A switchable coupling is placed between the drain of the input FETs of each amplifier within the amplifier circuit configuration. During split mode, the coupling is added to the circuit to allow some of the signal present at the drain of each input FET to be coupled to the drain of the other input FET.

An amplifier circuit configuration capable of processing non-contiguous intra-band carrier aggregate (CA) signals using amplifiers is disclosed herein. In some cases, each of a plurality of amplifiers is an amplifier configured as a cascode (i.e., a two-stage amplifier having two transistors, the first configured as a common source input transistor, e.g., input field effect transistor (FET), and the second configured in a common gate configuration as a cascode output transistor, (e.g. cascode output FET). In other embodiments, the amplifier may have additional transistors (i.e., more than two stages and/or stacked transistors). The amplifier circuit configuration can be operated in either single mode or split mode. A switchable coupling is placed between the drain of the input FETs of each amplifier within the amplifier circuit configuration. During split mode, the coupling is added to the circuit to allow some of the signal present at the drain of each input FET to be coupled to the drain of the other input FET.

The present invention relates to a four-way Doherty amplifier. The invention further relates to a mobile telecommunications base station. The invention proposes a new Doherty combiner topology that allows peak efficiencies to be reached at deeper back-off levels than conventional Doherty combiners.

The present invention relates to a four-way Doherty amplifier. The invention further relates to a mobile telecommunications base station. The invention proposes a new Doherty combiner topology that allows peak efficiencies to be reached at deeper back-off levels than conventional Doherty combiners.

A multistage amplifier includes: N amplifiers (N2), a (k+1).sup.th amplifier cascaded to a k.sup.th amplifier (1kN1), and each amplifier being configured to amplify a multicarrier signal; and an extraction circuit including an input and an output, the input being connected to an output of a j.sup.th amplifier (1jN1), and the output providing a compensation signal to an input of a (j+1).sup.th amplifier or an output of the (j+1).sup.th amplifier. The extraction circuit includes a filter circuit connected to the output of the j.sup.th amplifier that extracts a distortion frequency component of n times a differential frequency f2f1 (n1), a phase shifter cascaded to the filter circuit that shifts a phase of the component, and a gain adjustment circuit cascaded to the phase shifter that adjusts an amplitude of the component and generates the compensation signal.

A multistage amplifier includes: N amplifiers (N2), a (k+1).sup.th amplifier cascaded to a k.sup.th amplifier (1kN1), and each amplifier being configured to amplify a multicarrier signal; and an extraction circuit including an input and an output, the input being connected to an output of a j.sup.th amplifier (1jN1), and the output providing a compensation signal to an input of a (j+1).sup.th amplifier or an output of the (j+1).sup.th amplifier. The extraction circuit includes a filter circuit connected to the output of the j.sup.th amplifier that extracts a distortion frequency component of n times a differential frequency f2f1 (n1), a phase shifter cascaded to the filter circuit that shifts a phase of the component, and a gain adjustment circuit cascaded to the phase shifter that adjusts an amplitude of the component and generates the compensation signal.

A power amplifier and method for operating the same is disclosed. The amplifier includes a number of transistors coupled in series between a power node and a ground node. These transistors include a first transistor having a source terminal coupled to the power node, and a second transistor having its source terminal coupled to a ground node. A subset of transistors is also coupled in series between the first and second transistors. During operation in a first mode, the first and second transistors act as switching transistors, switching according to data received thereby. The subset of transistors, during the first mode, act as cascode transistors. During a second mode of operation, the transistors of the subset act as switching transistors, switching in accordance with the received data.