Patent classifications
H03F3/193
Power supply device
A current fluctuating due to a load fluctuation is limited to protect a semiconductor switch. A protection circuit includes a switch circuit that turns on when a predetermined conduction voltage is applied thereto, and a sub-reactance circuit having a predetermined reactance value is connected in parallel to a main reactance circuit through which a high frequency current generated by a semiconductor switch flows. When the switch circuit is turned on, the main reactance circuit and the sub-reactance circuit are connected in parallel, and a high frequency current flows through this parallel connection circuit. The impedance value of the parallel connection circuit is set to be larger than the impedance value of the main reactance circuit so that the current is limited due to the turning on of the switch circuit, and thus, the semiconductor switch is protected.
Power supply device
A current fluctuating due to a load fluctuation is limited to protect a semiconductor switch. A protection circuit includes a switch circuit that turns on when a predetermined conduction voltage is applied thereto, and a sub-reactance circuit having a predetermined reactance value is connected in parallel to a main reactance circuit through which a high frequency current generated by a semiconductor switch flows. When the switch circuit is turned on, the main reactance circuit and the sub-reactance circuit are connected in parallel, and a high frequency current flows through this parallel connection circuit. The impedance value of the parallel connection circuit is set to be larger than the impedance value of the main reactance circuit so that the current is limited due to the turning on of the switch circuit, and thus, the semiconductor switch is protected.
Method and apparatus of an input resistance of a passive mixer to broaden the input matching bandwidth of a common source/gate LNA
A common-source Low Noise Amplifier (LNA) comprises a first spiral inductor coupled to a source of a first transistor, a second spiral inductor coupled to a drain of a second transistor, and a third inductor connecting the first transistor to the second transistor. The third inductor is configurable to enable a first capacitance to be coupled in parallel to form a bandpass filter. The first spiral inductor is configurable to enable a second capacitance to be coupled in parallel to form a resonant circuit. A variation of the LNA further includes a drain of a third transistor coupled to a gate of a fourth transistor with a first width, a source of the third transistor coupled to the resonant circuit, and an oscillator clock configured to operate at a first frequency that enables the third transistor, wherein the third transistor presents a first impedance to the resonant circuit, causing the resonant circuit to have a first bandwidth.
Method and apparatus of an input resistance of a passive mixer to broaden the input matching bandwidth of a common source/gate LNA
A common-source Low Noise Amplifier (LNA) comprises a first spiral inductor coupled to a source of a first transistor, a second spiral inductor coupled to a drain of a second transistor, and a third inductor connecting the first transistor to the second transistor. The third inductor is configurable to enable a first capacitance to be coupled in parallel to form a bandpass filter. The first spiral inductor is configurable to enable a second capacitance to be coupled in parallel to form a resonant circuit. A variation of the LNA further includes a drain of a third transistor coupled to a gate of a fourth transistor with a first width, a source of the third transistor coupled to the resonant circuit, and an oscillator clock configured to operate at a first frequency that enables the third transistor, wherein the third transistor presents a first impedance to the resonant circuit, causing the resonant circuit to have a first bandwidth.
Apparatus and methods for oscillation suppression of cascode power amplifiers
Apparatus and methods for oscillation suppression of cascode power amplifiers are provided herein. In certain implementations, a power amplifier system includes a cascode power amplifier including a plurality of transconductance devices that operate in combination with a plurality of cascode devices to amplify a radio frequency input signal. The power amplifier system further includes a bias circuit that biases the plurality of cascode devices with two or more bias voltages that are decoupled from one another at radio frequency to thereby inhibit the cascode power amplifier from oscillating.
Apparatus and methods for oscillation suppression of cascode power amplifiers
Apparatus and methods for oscillation suppression of cascode power amplifiers are provided herein. In certain implementations, a power amplifier system includes a cascode power amplifier including a plurality of transconductance devices that operate in combination with a plurality of cascode devices to amplify a radio frequency input signal. The power amplifier system further includes a bias circuit that biases the plurality of cascode devices with two or more bias voltages that are decoupled from one another at radio frequency to thereby inhibit the cascode power amplifier from oscillating.
Switch-mode power amplifier for an RF transmitter employing digitally-controlled OOB harmonic attenuation techniques
The present document describes a digital power amplifier configured to provide an amplified output signal at an output port based on an input signal. The power amplifier comprises a drive unit configured to generate a high side drive signal comprising a sequence of pulses for controlling the high side switch and a low side drive signal comprising a sequence of pulses for controlling the low side switch, respectively. The drive signals are generated such that the pulses of the high side drive signal are non-overlapping with regards to the pulses of the low side drive signal, and such that the sequence of pulses of the high side drive signal and the sequence of pulses of the low side drive signal have a reduced fraction of energy from higher order harmonics compared to a sequence of rectangular shaped pulses.
Switch-mode power amplifier for an RF transmitter employing digitally-controlled OOB harmonic attenuation techniques
The present document describes a digital power amplifier configured to provide an amplified output signal at an output port based on an input signal. The power amplifier comprises a drive unit configured to generate a high side drive signal comprising a sequence of pulses for controlling the high side switch and a low side drive signal comprising a sequence of pulses for controlling the low side switch, respectively. The drive signals are generated such that the pulses of the high side drive signal are non-overlapping with regards to the pulses of the low side drive signal, and such that the sequence of pulses of the high side drive signal and the sequence of pulses of the low side drive signal have a reduced fraction of energy from higher order harmonics compared to a sequence of rectangular shaped pulses.
Switchless multi input stacked transistor amplifier tree structure
Methods and devices for amplifying a plurality of input RF signals based on a multi-input cascode configuration is described. Transistors of stages of the multi-input cascode configuration are connected according to a tree, where there is at least one cascode transistor that is connected to at least two transistors of a stage below. In one case the stage below is an input stage, and in another case the stage below is a cascode stage. Activation and deactivation of transistors of the stages provide different conduction paths between the input stage and an output stage.
Switchless multi input stacked transistor amplifier tree structure
Methods and devices for amplifying a plurality of input RF signals based on a multi-input cascode configuration is described. Transistors of stages of the multi-input cascode configuration are connected according to a tree, where there is at least one cascode transistor that is connected to at least two transistors of a stage below. In one case the stage below is an input stage, and in another case the stage below is a cascode stage. Activation and deactivation of transistors of the stages provide different conduction paths between the input stage and an output stage.