A method for harmonic trapping in a matching network of a power amplifier includes determining primary inductance and secondary inductance of a differential transformer of the matching network, based on a signal operating frequency of the power amplifier. An inductance value for an L-C filter is determined based on the secondary inductance and a harmonic frequency of a local oscillator (LO) signal. A capacitance value for the L-C filter is determined based on the inductance value and the harmonic frequency of the LO signal. The L-C filter is provided on an electric connection between a direct current (DC) bias voltage source and a secondary inductor of the differential transformer. The L-C filter is configured with the determined inductance value and the determined capacitance value.

Described are an amplifier circuits, systems, and methods for amplifying a plurality of sinusoid signals having a relative phase difference to each other. The amplifier circuit comprises a first sequence of at least three transistor amplifiers, wherein a first terminal of each transistor amplifier of the first sequence is configured to receive one respective signal of the plurality sinusoid signals. The amplifier further comprises a second sequence of at least three transistor amplifiers. A second terminal of each transistor amplifier of the second sequence is connected to a third terminal of one respective transistor amplifier of the first sequence. A first terminal of each transistor amplifier of the second sequence is connected to the third terminal of a next transistor amplifier of the second sequence. The first terminal of a last transistor amplifier is connected to the third terminal of a first transistor amplifier.

Described are an amplifier circuits, systems, and methods for amplifying a plurality of sinusoid signals having a relative phase difference to each other. The amplifier circuit comprises a first sequence of at least three transistor amplifiers, wherein a first terminal of each transistor amplifier of the first sequence is configured to receive one respective signal of the plurality sinusoid signals. The amplifier further comprises a second sequence of at least three transistor amplifiers. A second terminal of each transistor amplifier of the second sequence is connected to a third terminal of one respective transistor amplifier of the first sequence. A first terminal of each transistor amplifier of the second sequence is connected to the third terminal of a next transistor amplifier of the second sequence. The first terminal of a last transistor amplifier is connected to the third terminal of a first transistor amplifier.

Provided herein are amplifiers, such as buffers, with increased headroom. An amplifier stage includes a follower transistor and current source configured to receive a power supply voltage comprising an alternating current component and a direct current component. The alternating current component of the power supply voltage has substantially the same frequency and magnitude as the input signal received by the follower transistor. In radio frequency (RF) and intermediate frequency (IF) buffer applications, for example, the increased headroom can allow for linear buffering of an input signals with increased amplitude so that the output power one decibel (OP1dB) compression point can be increased.

Provided herein are amplifiers, such as buffers, with increased headroom. An amplifier stage includes a follower transistor and current source configured to receive a power supply voltage comprising an alternating current component and a direct current component. The alternating current component of the power supply voltage has substantially the same frequency and magnitude as the input signal received by the follower transistor. In radio frequency (RF) and intermediate frequency (IF) buffer applications, for example, the increased headroom can allow for linear buffering of an input signals with increased amplitude so that the output power one decibel (OP1dB) compression point can be increased.

An amplifier according to an embodiment of the present invention includes a first transistor and a second transistor that are connected between a ground point and a power supply. A control terminal of the first transistor is connected to an input terminal. A first terminal of the first transistor is connected to the ground point. A second terminal of the second transistor is connected to an output terminal. The amplifier further includes an impedance element and a variable resistance unit. The impedance element is connected between the second terminal of the second transistor and the power supply. The variable resistance unit is connected between the second terminal of the first transistor and the first terminal of the second transistor.

A driver interface for a switch-based circuit includes an AC coupling capacitor, a first diode or a first series of diodes, and a second diode or a second series of diodes connected in series with the first diode or first series of diodes but with an opposing polarity. The AC coupling capacitor removes a DC voltage from an input bi-level drive signal that does not have the appropriate high and low drive levels needed to switch a FET in the switch-based circuit between fully ON and fully OFF states. The first diode or first series of diodes and the second diode or second series of diodes clamp the resulting AC-coupled drive signal to produce an output bi-level drive signal having the high and low drive levels needed to switch the FET between fully ON and fully OFF states. The driver interface maintains the high and low drive levels of the output bi-level drive signal irrespective of any changes made to the duty cycle or pulse density of the input bi-level drive signal.

A driver interface for a switch-based circuit includes an AC coupling capacitor, a first diode or a first series of diodes, and a second diode or a second series of diodes connected in series with the first diode or first series of diodes but with an opposing polarity. The AC coupling capacitor removes a DC voltage from an input bi-level drive signal that does not have the appropriate high and low drive levels needed to switch a FET in the switch-based circuit between fully ON and fully OFF states. The first diode or first series of diodes and the second diode or second series of diodes clamp the resulting AC-coupled drive signal to produce an output bi-level drive signal having the high and low drive levels needed to switch the FET between fully ON and fully OFF states. The driver interface maintains the high and low drive levels of the output bi-level drive signal irrespective of any changes made to the duty cycle or pulse density of the input bi-level drive signal.

The disclosure provides a circuit. The circuit includes a gain stage block. The gain stage block is coupled to an input voltage through a first switch. A first capacitor is coupled between the first switch and a ground terminal. A second capacitor is coupled between the first switch and a second switch. A third switch is coupled between the second capacitor and a fixed terminal of the gain stage block.

An amplifier, communication device and method of amplification are disclosed. An RF signal is amplified by a Doherty power amplifier (DPA). The DPA has a main amplifier with a Class-AB amplifier in parallel with a Class-C amplifier. When the RF signal power is smaller than 6 dB PBO, the Class-AB amplifier provides the main amplifier amplification; when the RF signal is between 6 dB PBO and 0 dB PBO, both the Class-AB and Class-C amplifiers provide the main amplifier amplification.