A transformer is provided. The transformer includes at least one first primary turn; at least one second primary turn; and a first secondary turn and a second secondary turn. The first secondary turn and the second secondary turn are arranged laterally between the at least one first primary turn and the at least one second primary turn. The first secondary turn and the second secondary turn are arranged one above the other.

An RF transistor amplifier circuit comprises a Group III nitride based RF transistor amplifier having a gate terminal, a Group III nitride based self-bias circuit that includes a first Group III nitride based depletion mode high electron mobility transistor, the Group III nitride based self-bias circuit configured to generate a bias voltage, and a Group III nitride based depletion mode differential amplifier that is configured to generate an inverted bias voltage from the bias voltage and to apply the inverted bias voltage to the gate terminal of the Group III nitride based RF transistor amplifier. The Group III nitride based RF transistor amplifier, the Group III nitride based self-bias circuit and the Group III nitride based depletion mode differential amplifier are all implemented in a single die.

An RF transistor amplifier circuit comprises a Group III nitride based RF transistor amplifier having a gate terminal, a Group III nitride based self-bias circuit that includes a first Group III nitride based depletion mode high electron mobility transistor, the Group III nitride based self-bias circuit configured to generate a bias voltage, and a Group III nitride based depletion mode differential amplifier that is configured to generate an inverted bias voltage from the bias voltage and to apply the inverted bias voltage to the gate terminal of the Group III nitride based RF transistor amplifier. The Group III nitride based RF transistor amplifier, the Group III nitride based self-bias circuit and the Group III nitride based depletion mode differential amplifier are all implemented in a single die.

A method of operating a monolithic microwave integrated circuit (MMIC) in a radar transmitter includes: sending a radio frequency (RF) signal to a power amplifier of the radar transmitter, where the power amplifier is controlled by a termination control signal, where when the termination control signal is de-asserted, the power amplifier is configured to pass the RF signal through the power amplifier for transmission by an RF antenna, where when the termination control signal is asserted, the power amplifier is configured to terminate the RF signal in the power amplifier; transmitting the RF signal by de-asserting the termination control signal; and after de-asserting the termination control signal, disabling transmission of the RF signal by: reducing a power of the RF signal; and asserting the termination control signal.

Various methods and circuital arrangements for biasing one or more gates of stacked transistors of an amplifier are possible where the amplifier is configured to operate in at least an active mode and a standby mode. Circuital arrangements can reduce bias circuit standby current during operation in the standby mode while allowing a quick recovery to normal operating conditions of the amplifier. Biasing an input transistor of the stacked transistors can be obtained by using a replica stack circuit.

Various methods and circuital arrangements for biasing one or more gates of stacked transistors of an amplifier are possible where the amplifier is configured to operate in at least an active mode and a standby mode. Circuital arrangements can reduce bias circuit standby current during operation in the standby mode while allowing a quick recovery to normal operating conditions of the amplifier. Biasing an input transistor of the stacked transistors can be obtained by using a replica stack circuit.

Methods and devices to improve nonlinearity performance of low noise amplifiers (LNAs) are disclosed. The described methods and devices reduce the capacitive loading of the LNA amplifying devices on the bypass path of the LNAs when operating in the bypass mode. This is performed by decoupling the active devices from ground to put the amplifying devices in a floating state, thus minimizing the impact of the gate-source capacitances of the amplifying devices on the overall linear performance of the LNA operating in the bypass mode.

A complementary balanced low-noise amplifier is disclosed. In one aspect, the low-noise amplifier (LNA) may be a single-ended cascoded complementary common-source LNA that is capable of operating in low-power conditions. In particular, the LNA may include a first path with a common-source amplifier formed from an N-type material and a second path with a common-source amplifier formed from a P-type material that collectively form a complementary common-source amplifier. By providing two paths in the complementary amplifier, headroom may be preserved for output transistors. Additionally, higher-order intercept points (e.g., IP2 or IP3) characteristics have better performance profiles resulting in better overall performance and improved user experience.

A semiconductor device includes: a first semiconductor layer formed, on a substrate, of a nitride semiconductor; a second semiconductor layer formed, on the first semiconductor layer, of a nitride semiconductor; a source electrode formed on the second semiconductor layer; a drain electrode formed on the second semiconductor layer; a metal oxide film formed, between the source electrode and the drain electrode, on the second semiconductor layer; and a gate electrode formed on the metal oxide film. The metal oxide film includes AlO.sub.x and InO.sub.x. AlO.sub.x/InO.sub.x in the metal oxide film is greater than or equal to 3.

A semiconductor device includes: a first semiconductor layer formed, on a substrate, of a nitride semiconductor; a second semiconductor layer formed, on the first semiconductor layer, of a nitride semiconductor; a source electrode formed on the second semiconductor layer; a drain electrode formed on the second semiconductor layer; a metal oxide film formed, between the source electrode and the drain electrode, on the second semiconductor layer; and a gate electrode formed on the metal oxide film. The metal oxide film includes AlO.sub.x and InO.sub.x. AlO.sub.x/InO.sub.x in the metal oxide film is greater than or equal to 3.