A current reuse FET amplifier according to the present invention provides an effect of reducing a variation of bias current of the amplifier, with gate voltage or a resistor for self-biasing of an FET of the amplifier changing in accordance with a process variation of saturation current Idss of the FET.

A current reuse FET amplifier according to the present invention provides an effect of reducing a variation of bias current of the amplifier, with gate voltage or a resistor for self-biasing of an FET of the amplifier changing in accordance with a process variation of saturation current Idss of the FET.

A two-stage amplifier of a type of the current re-use configuration is disclosed. The amplifier includes first to third transistors, where the first transistor constitute the first stage, while, the latter two transistors constitute the second stance. The first to third transistors are connected in series between a power supply and ground such that a bias current supplied to the third transistor flows in the second and first transistors. The first transistor in the source thereof is grounded in the DC mode. The second transistor is grounded in the AC mode but floated in the DC mode. The third transistor that outputs an amplified signal is connected in parallel in the AC mode but in series in the DC mode with respect to the second transistor.

A two-stage amplifier of a type of the current re-use configuration is disclosed. The amplifier includes first to third transistors, where the first transistor constitute the first stage, while, the latter two transistors constitute the second stance. The first to third transistors are connected in series between a power supply and ground such that a bias current supplied to the third transistor flows in the second and first transistors. The first transistor in the source thereof is grounded in the DC mode. The second transistor is grounded in the AC mode but floated in the DC mode. The third transistor that outputs an amplified signal is connected in parallel in the AC mode but in series in the DC mode with respect to the second transistor.

A high frequency amplifier includes a high frequency amplifier transistor integrated in a first die of a first semiconductor technology and a matching circuit. The high frequency amplifier transistor has an input terminal, an output terminal and a reference terminal. The reference terminal is coupled to a reference potential. The matching circuit includes at least a first inductive bondwire, a second inductive bondwire and a capacitive element arranged in series with said inductive bondwires. The capacitive element is integrated in a second die of a second semiconductor technology different from the first semiconductor technology. The second semiconductor technology includes an isolating substrate for conductively isolating the capacitive element from a support attached at a first side to the second die. The capacitive element includes a first plate electrically coupled to a first bondpad of the second die and a second plate electrically coupled to a second bondpad of the second die.

A high frequency amplifier includes a high frequency amplifier transistor integrated in a first die of a first semiconductor technology and a matching circuit. The high frequency amplifier transistor has an input terminal, an output terminal and a reference terminal. The reference terminal is coupled to a reference potential. The matching circuit includes at least a first inductive bondwire, a second inductive bondwire and a capacitive element arranged in series with said inductive bondwires. The capacitive element is integrated in a second die of a second semiconductor technology different from the first semiconductor technology. The second semiconductor technology includes an isolating substrate for conductively isolating the capacitive element from a support attached at a first side to the second die. The capacitive element includes a first plate electrically coupled to a first bondpad of the second die and a second plate electrically coupled to a second bondpad of the second die.

Embodiments of radio frequency (RF) front-end circuitry are disclosed where the RF front-end circuitry includes a tunable RF filter structure and a calibration circuit. The tunable RF filter structure includes (at least) a pair of weakly coupled resonators and defines a transfer function with a passband. The calibration circuit is configured to shape the passband so that the passband defines a center frequency. Additionally, the calibration circuit is configured to detect a phase difference at the target center frequency between the pair of weakly coupled resonators and adjust the phase difference of the pair of weakly coupled resonators at the target center frequency so as to reduce a frequency displacement between the center frequency of the passband and the target center frequency. In this manner, the calibration circuit calibrates the tunable RF filter structure to correct for errors in the center frequency of the passband due to component manufacturing variations.

Embodiments of radio frequency (RF) front-end circuitry are disclosed where the RF front-end circuitry includes a tunable RF filter structure and a calibration circuit. The tunable RF filter structure includes (at least) a pair of weakly coupled resonators and defines a transfer function with a passband. The calibration circuit is configured to shape the passband so that the passband defines a center frequency. Additionally, the calibration circuit is configured to detect a phase difference at the target center frequency between the pair of weakly coupled resonators and adjust the phase difference of the pair of weakly coupled resonators at the target center frequency so as to reduce a frequency displacement between the center frequency of the passband and the target center frequency. In this manner, the calibration circuit calibrates the tunable RF filter structure to correct for errors in the center frequency of the passband due to component manufacturing variations.

An apparatus includes an input port, an output port, and a plurality of amplifier stages connected in parallel between the input port and the output port. Each of the amplifier stages comprises a common source field effect transistor (CSFET) and at least two common gate field effect transistors (CGFETs) coupled in series with a drain of the common source FET. At least one of the common gate field effect transistors of each stage includes a stabilizing network connected between drain and source diffusions.

An apparatus includes an input port, an output port, and a plurality of amplifier stages connected in parallel between the input port and the output port. Each of the amplifier stages comprises a common source field effect transistor (CSFET) and at least two common gate field effect transistors (CGFETs) coupled in series with a drain of the common source FET. At least one of the common gate field effect transistors of each stage includes a stabilizing network connected between drain and source diffusions.