An amplifier circuit configuration capable of processing non-contiguous intra-band carrier aggregate (CA) signals using amplifiers is disclosed herein. In some cases, each of a plurality of amplifiers is an amplifier configured as a cascode (i.e., a two-stage amplifier having two transistors, the first configured as a “common source” input transistor, e.g., input field effect transistor (FET), and the second configured in a “common gate” configuration as a cascode output transistor, (e.g. cascode output FET). In other embodiments, the amplifier may have additional transistors (i.e., more than two stages and/or stacked transistors). The amplifier circuit configuration can be operated in either single mode or split mode. A switchable coupling is placed between the drain of the input FETs of each amplifier within the amplifier circuit configuration. During split mode, the coupling is added to the circuit to allow some of the signal present at the drain of each input FET to be coupled to the drain of the other input FET.

A power amplifier device includes: a first power supply terminal for inputting a first power supply voltage; a first transistor for power amplification that (i) includes a first gate to which a bias voltage is applied, and (ii) is supplied with power from the first power supply terminal; a second power supply terminal for inputting a second power supply voltage lower than the first power supply voltage; a second transistor for monitoring that (i) includes a second gate to which the bias voltage is applied, (ii) is supplied with power from the first power supply terminal or the second power supply terminal, and (iii) imitates an operation of the first transistor; and a bias circuit that is supplied with power from the second power supply terminal and generates and adjusts the bias voltage according to a drain current or a source current of the second transistor.

The present disclosure provides a multiple output low noise amplifier circuit, chip and electronic device. The multiple output low noise amplifier circuit includes: a first processing module for amplifying an input voltage signal and converting it into at least two first current signals; a second processing module for impedance matching at the input terminal of the low noise amplifier circuit, and for amplifying the input voltage signal and converting it into at least two second current signals; a voltage output module, connected to the first processing module and the second processing module, for combining the first current signals and the second current signals and converting them into output voltage signals. The low noise amplifier circuit can convert a single input voltage signal to at least two output voltage signals, and is applicable in RF front ends with multiple output terminals.

The present disclosure provides a multiple output low noise amplifier circuit, chip and electronic device. The multiple output low noise amplifier circuit includes: a first processing module for amplifying an input voltage signal and converting it into at least two first current signals; a second processing module for impedance matching at the input terminal of the low noise amplifier circuit, and for amplifying the input voltage signal and converting it into at least two second current signals; a voltage output module, connected to the first processing module and the second processing module, for combining the first current signals and the second current signals and converting them into output voltage signals. The low noise amplifier circuit can convert a single input voltage signal to at least two output voltage signals, and is applicable in RF front ends with multiple output terminals.

The present disclosure provides a Multiple Inputs Multiple Ouputs RF front-end amplifier circuit, chip, and electronic device and a method for configuring signal path. The RF front-end amplifier circuit includes: at least two low-noise amplifying modules, each of which amplifies one voltage signal and converts into one or more intermediate current signals; a voltage output module, connected to each of the low-noise amplifying modules, for combining the intermediate current signal output by the low-noise amplifying module and converting them into one or more output voltage signals. The RF front-end amplifier circuit can be applied to an RF front-end with a Multiple Inputs Multiple Outputs structure.

The present disclosure provides a Multiple Inputs Multiple Ouputs RF front-end amplifier circuit, chip, and electronic device and a method for configuring signal path. The RF front-end amplifier circuit includes: at least two low-noise amplifying modules, each of which amplifies one voltage signal and converts into one or more intermediate current signals; a voltage output module, connected to each of the low-noise amplifying modules, for combining the intermediate current signal output by the low-noise amplifying module and converting them into one or more output voltage signals. The RF front-end amplifier circuit can be applied to an RF front-end with a Multiple Inputs Multiple Outputs structure.

An amplifier circuit includes an input terminal, an output terminal, an amplifier including a first transistor and a second transistor that are connected in parallel, a first capacitor, and a second capacitor, and an inductor. Each of the first transistor and the second transistor has a gate connected to the input terminal, a source connected to ground, and a drain connected to the output terminal. The inductor is provided between the input terminal and a node of parallel connection of the first transistor and the second transistor on the side of the input terminal. The first capacitor is arranged in a path connecting the node and the gate of the first transistor, the second capacitor is arranged in a path connecting the node and the gate of the second transistor, and the capacitance of the first capacitor differs from the capacitance of the second capacitor.

Bias circuits and methods for silicon-based amplifier architectures that are tolerant of supply and bias voltage variations, bias current variations, and transistor stack height, and compensate for poor output resistance characteristics. Embodiments include power amplifiers and low-noise amplifiers that utilize a cascode reference circuit to bias the final stages of a cascode amplifier under the control of a closed loop bias control circuit. The closed loop bias control circuit ensures that the current in the cascode reference circuit is approximately equal to a selected multiple of a known current value by adjusting the gate bias voltage to the final stage of the cascode amplifier. The final current through the cascode amplifier is a multiple of the current in the cascode reference circuit, based on a device scaling factor representing the relative sizes of the transistor devices in the cascode amplifier and in the cascode reference circuit.

Bias circuits and methods for silicon-based amplifier architectures that are tolerant of supply and bias voltage variations, bias current variations, and transistor stack height, and compensate for poor output resistance characteristics. Embodiments include power amplifiers and low-noise amplifiers that utilize a cascode reference circuit to bias the final stages of a cascode amplifier under the control of a closed loop bias control circuit. The closed loop bias control circuit ensures that the current in the cascode reference circuit is approximately equal to a selected multiple of a known current value by adjusting the gate bias voltage to the final stage of the cascode amplifier. The final current through the cascode amplifier is a multiple of the current in the cascode reference circuit, based on a device scaling factor representing the relative sizes of the transistor devices in the cascode amplifier and in the cascode reference circuit.

Modified forms of hemagglutinin (HA) protein including those with modified immunodominant regions and with modified maturation cleavage sites, and virus and virus-like particles containing them are disclosed.