An asymmetrical power amplifier circuit is provided. The asymmetrical power amplifier circuit includes a carrier amplifier and a peak amplifier. The carrier amplifier is always active to amplify a radio frequency (RF) to a carrier output power, while the peak amplifier is only active to amplify the RF signal to a peak output power when a time-variant output power of the RF signal is higher than a predefined power threshold. The RF signal in the carrier output power is summed with the RF signal in the peak output power to thereby output the amplified RF signal in the time-variant output power. Unlike a conventional symmetrical power amplifier, the carrier output power and the peak output power are different at a peak of the time-variant output power. As such, the carrier amplifier and the peak amplifier can both operate with optimal efficiency based on a same modulated voltage.

Various methods and circuital arrangements for biasing gates of stacked transistor amplifier that includes two series connected transistor stacks of different polarities are presented, where the amplifier is configured to operate according to different modes of operation. Such circuital arrangements operate in a closed loop with a feedback error voltage that is based on a sensed voltage at a common node of the two series connected transistor stacks. According to one aspect, gate biasing voltages to input transistors of each of the two series connected stacks are adjusted by respective current mirrors that are controlled based on the feedback error voltage. According to another aspect, other gate biasing voltages are generated by maintaining a fixed gate biasing voltage between any two consecutive gate basing voltages.

Various methods and circuital arrangements for biasing gates of stacked transistor amplifier that includes two series connected transistor stacks of different polarities are presented, where the amplifier is configured to operate according to different modes of operation. Such circuital arrangements operate in a closed loop with a feedback error voltage that is based on a sensed voltage at a common node of the two series connected transistor stacks. According to one aspect, gate biasing voltages to input transistors of each of the two series connected stacks are adjusted by respective current mirrors that are controlled based on the feedback error voltage. According to another aspect, other gate biasing voltages are generated by maintaining a fixed gate biasing voltage between any two consecutive gate basing voltages.

In one embodiment, an apparatus includes: a low noise amplifier (LNA) to receive and amplify a radio frequency (RF) signal, the LNA having a first controllable gain; a mixer to downconvert the RF signal to a second frequency signal; a programmable gain amplifier (PGA) coupled to the mixer to amplify the second frequency signal, the PGA having a second controllable gain; a digitizer to digitize the second frequency signal to a digitized signal; a demodulator coupled to the digitizer to demodulate the digitized signal; an automatic gain control (AGC) circuit to control one or more of the first controllable gain and the second controllable gain; and an AGC settling circuit to cause the demodulator to begin operation in response to determining that the AGC circuit has settled.

In one embodiment, an apparatus includes: a low noise amplifier (LNA) to receive and amplify a radio frequency (RF) signal, the LNA having a first controllable gain; a mixer to downconvert the RF signal to a second frequency signal; a programmable gain amplifier (PGA) coupled to the mixer to amplify the second frequency signal, the PGA having a second controllable gain; a digitizer to digitize the second frequency signal to a digitized signal; a demodulator coupled to the digitizer to demodulate the digitized signal; an automatic gain control (AGC) circuit to control one or more of the first controllable gain and the second controllable gain; and an AGC settling circuit to cause the demodulator to begin operation in response to determining that the AGC circuit has settled.

A power amplification system is provided comprising: a power amplifier circuit, the power amplifier circuit including a plurality of transistors; and a frequency response compensation circuit for providing a plurality of values of capacitance. The frequency response compensation circuit having at least one tuning capacitor. Each of the at least one tuning capacitors is coupled to a tuning switch for regulating the current path to and/or from the corresponding capacitor to control the value of the capacitance provided by the frequency response compensation circuit. The frequency response compensation circuit is coupled to at least two of the transistors of the power amplifier circuit. The frequency response compensation circuit is configured to reduce variation over frequency of a load impedance of the power amplification system. A wireless device comprising such a power amplification system is also provided. A wireless module comprising such a power amplification system is also provided.

A power amplification system is provided comprising: a power amplifier circuit; an output power control circuit for providing a plurality of values of capacitance, and a balun coupled to the power amplifier circuit and to the output power control circuit. The output power control circuit includes at least one load control capacitor. Each of the at least one load control capacitors is coupled to a load control switch for regulating the current path to and/or from the corresponding capacitor to control the value of the capacitance provided by the output power control circuit. A wireless device comprising such a power amplification system is also provided. A wireless module comprising such a power amplification system is also provided.

Amplification circuitry is disclosed that couples neutralization transistors to amplification transistors to neutralize parasitic capacitance of the amplification transistors. Gates of a first amplification transistor and a first neutralization transistor are coupled together, and gates of a second amplification transistor and a second neutralization transistor are also coupled together. Drains of the first amplification transistor and the second neutralization transistor are coupled together, and drains of the second amplification transistor and the first neutralization transistor are also coupled together. Sources of neutralization transistors are coupled together at a node, such that a voltage swing of a first signal in the first neutralization transistor may be canceled by a voltage swing of a second signal in the second neutralization transistor. The node also couples to a resistor that prevents charge building in the neutralization transistors.

Methods and circuital arrangements for turning OFF branches of a multi-branch cascode amplifier are presented. First and second switching arrangements coupled to a branch allow turning OFF the branch while protecting transistors of the branch from a supply voltage that may be greater than a tolerable voltage of the transistors. The first switching arrangement includes a transistor-based switch that is in series connection with the transistors of the branch. The first switching arrangement drops the supply voltage during the OFF state of the branch and provides a conduction path for a current through the branch during the ON state of the branch. A resistor and a shunting switch are coupled to a gate of the transistor-based switch to reduce parasitic coupling effects of the transistor-based switch upon an RF signal coupled to the branch during the ON state and OFF state of the branch.

Methods and circuital arrangements for turning OFF branches of a multi-branch cascode amplifier are presented. First and second switching arrangements coupled to a branch allow turning OFF the branch while protecting transistors of the branch from a supply voltage that may be greater than a tolerable voltage of the transistors. The first switching arrangement includes a transistor-based switch that is in series connection with the transistors of the branch. The first switching arrangement drops the supply voltage during the OFF state of the branch and provides a conduction path for a current through the branch during the ON state of the branch. A resistor and a shunting switch are coupled to a gate of the transistor-based switch to reduce parasitic coupling effects of the transistor-based switch upon an RF signal coupled to the branch during the ON state and OFF state of the branch.