An amplification circuit includes a filter circuit, an amplifier, a capacitor, a bypass line, and a switch circuit that includes a first FET and a second FET connected in series between one end and the other end of the bypass line, a first resistance element connected in series to a gate of the first FET, and a second resistance element connected in series to a gate of the second FET. A first control signal is supplied to the gate of the first FET. A second control signal is supplied to the gate of the second FET. A product of a gate length and a gate width of the first FET and a resistance value of the first resistance element is smaller than a product of a gate length and a gate width of the second FET and a resistance value of the second resistance element.

One example includes a device that is comprised of a pre-power amplifier, a power amplifier, a signal path, and a dynamic bias circuit. The pre-power amplifier amplifies an input signal and outputs a first amplified signal. The power amplifier receives the first amplified signal and amplifies the first amplified signal based on a dynamic bias signal to produce a second amplified signal at an output thereof. The signal path is coupled between an output of the pre-power amplifier and an input of the power amplifier. The dynamic bias circuit monitors the first amplified signal, generates the dynamic bias signal, and outputs the dynamic bias into the signal path.

One example includes a device that is comprised of a pre-power amplifier, a power amplifier, a signal path, and a dynamic bias circuit. The pre-power amplifier amplifies an input signal and outputs a first amplified signal. The power amplifier receives the first amplified signal and amplifies the first amplified signal based on a dynamic bias signal to produce a second amplified signal at an output thereof. The signal path is coupled between an output of the pre-power amplifier and an input of the power amplifier. The dynamic bias circuit monitors the first amplified signal, generates the dynamic bias signal, and outputs the dynamic bias into the signal path.

Methods and apparatuses for controlling impedance in intermediate nodes of a stacked FET amplifier are presented. According to one aspect, a series-connected resistive and capacitive network coupled to a gate of a cascode FET transistor of the amplifier provide control of a real part and an imaginary part of an impedance looking into a source of the transistor. According to another aspect, a second parallel-connected resistive and inductive network coupled to the first network provide further control of the real and imaginary parts of the impedance. According to another aspect, a combination of the first and/or the second networks provide control of the impedance to cancel a reactance component of the impedance. According to another aspect, such combination provides control of the real part for distribution of an RF voltage output by the amplifier across stacked FET transistors of the amplifier.

Gallium nitride based RF transistor amplifiers include a semiconductor structure having a gallium nitride based channel layer and a gallium nitride based barrier layer thereon, and are configured to operate at a specific direct current drain-to-source bias voltage. These amplifiers are configured to have a normalized drain-to-gate capacitance at the direct current drain-to-source bias voltage, and to have a second normalized drain-to-gate capacitance at two-thirds the direct current drain-to-source bias voltage, where the second normalized drain-to-gate capacitance is less than twice the first normalized drain-to-gate capacitance.

Gallium nitride based RF transistor amplifiers include a semiconductor structure having a gallium nitride based channel layer and a gallium nitride based barrier layer thereon, and are configured to operate at a specific direct current drain-to-source bias voltage. These amplifiers are configured to have a normalized drain-to-gate capacitance at the direct current drain-to-source bias voltage, and to have a second normalized drain-to-gate capacitance at two-thirds the direct current drain-to-source bias voltage, where the second normalized drain-to-gate capacitance is less than twice the first normalized drain-to-gate capacitance.

An amplification circuit includes a switch circuit, an amplifier, and a control circuit. The switch circuit has a first terminal coupled to a radio frequency signal input terminal or a system voltage terminal, a second terminal coupled to an input terminal of the amplifier, and a control terminal configured to receive a control signal. The amplifier amplifies a radio frequency signal. The control circuit generates the control signal according to a driving current generated by the amplifier. When the control circuit determines that the amplifier operates in a high power mode, the control circuit controls the control signal to adjust a conducting level between the first terminal and the second terminal of the switch circuit according to the intensity of the driving current.

A radio frequency circuit has an amplifier that amplifies an input radio frequency signal, a power supply path that is disposed between an output node of the amplifier and a power supply node to which a DC bias voltage is supplied, and includes a first inductor and a second inductor connected in series, a first resonator that comprises a third inductor and a first capacitor connected in series to the third inductor, and resonates at a series resonance frequency, a second resonator that resonates at a series resonance frequency corresponding to an inductance of the first inductor, a capacitance of the second capacitor, and a resistance value of the first resistor, and a third resonator that comprises a third capacitor connected in parallel with the second inductor, and resonates at a parallel resonance frequency corresponding to a capacitance of the third capacitor and an inductance of the second inductor.

A radio frequency circuit has an amplifier that amplifies an input radio frequency signal, a power supply path that is disposed between an output node of the amplifier and a power supply node to which a DC bias voltage is supplied, and includes a first inductor and a second inductor connected in series, a first resonator that comprises a third inductor and a first capacitor connected in series to the third inductor, and resonates at a series resonance frequency, a second resonator that resonates at a series resonance frequency corresponding to an inductance of the first inductor, a capacitance of the second capacitor, and a resistance value of the first resistor, and a third resonator that comprises a third capacitor connected in parallel with the second inductor, and resonates at a parallel resonance frequency corresponding to a capacitance of the third capacitor and an inductance of the second inductor.

A noise detecting circuit including an amplifier circuit, a filtering circuit and a comparing circuit. The amplifier circuit is arranged to amplify an input signal and output an amplified signal, wherein the input signal is received from a circuit to be detected and indicates a noise level of the circuit to be detected. The filtering circuit is coupled to the amplifier circuit and arranged to filter the amplified signal and output a filtered signal. The comparing circuit is coupled to the filtering circuit and arranged to compare the filtered signal to a reference voltage and output an output signal indicating the noise level of the circuit to be detected.