Systems with object detection capabilities may include a radio detection and ranging (RADAR) system. The RADAR system or other portions of the systems may include analog-to-digital converter circuitry. The analog-to-digital converter circuitry may be implemented as pipeline analog-to-digital converter circuitry having multiple stages. Each stage may include multiplying digital-to-analog converter circuitry having a sampling network and amplifier circuitry. The amplifier circuitry may be implemented as a two-stage amplifier. One or more transistors in the two-stage amplifier may receive adaptive control signals that counteract bias current changes across the one or more transistors due to supply voltage changes.

A power amplifying circuit includes a first amplifying unit that amplifies a first radio-frequency signal and a second amplifying unit that amplifies a second radio-frequency signal. The first amplifying unit includes a first matching circuit that performs impedance matching for a circuit in a preceding stage, and a first amplifying circuit that amplifies the first radio-frequency signal that has passed through the first matching circuit. The second amplifying unit includes a second matching circuit that performs impedance matching for the circuit in the preceding stage, a resistor including a first end and a second end, the first end being electrically connected to the second matching circuit, and a second amplifying circuit that is electrically connected to the second end of the resistor and that amplifies the second radio-frequency signal that has passed through the resistor.

A power amplifying circuit includes a first amplifying unit that amplifies a first radio-frequency signal and a second amplifying unit that amplifies a second radio-frequency signal. The first amplifying unit includes a first matching circuit that performs impedance matching for a circuit in a preceding stage, and a first amplifying circuit that amplifies the first radio-frequency signal that has passed through the first matching circuit. The second amplifying unit includes a second matching circuit that performs impedance matching for the circuit in the preceding stage, a resistor including a first end and a second end, the first end being electrically connected to the second matching circuit, and a second amplifying circuit that is electrically connected to the second end of the resistor and that amplifies the second radio-frequency signal that has passed through the resistor.

An amplifier includes a first coil coupled to at least one input node. The amplifier further includes second and third coils. A first terminal of the second coil is coupled to a source terminal of a first transistor, while a second terminal of the second coil is coupled to a source terminal of a second transistor. A third coil includes first and second terminals coupled to gate terminals of the first and second transistors, respectively. Responsive to receiving an input signal, the first coil electromagnetically conveys the signal to the second and third coils.

A Doherty amplifier is disclosed with a main amplifier having a main input in communication with a radio frequency (RF) signal input and a main output in communication with a RF signal output. Also included is a peaking amplifier having a peak input in communication with the RF signal input and a peak output in communication with the RF signal input. Further included is main neutralization circuitry having a main neutralization input in communication with the peak input and a main neutralization output in communication with the main input, wherein the main neutralization circuitry is configured to inject a main neutralization signal into the main input such that the main neutralization signal is 180°±10% out of phase and equal in amplitude to within ±10% of a main parasitic feedback signal passed from the main output to the main input by way of a main parasitic feedback capacitance.

A Doherty amplifier is disclosed with a main amplifier having a main input in communication with a radio frequency (RF) signal input and a main output in communication with a RF signal output. Also included is a peaking amplifier having a peak input in communication with the RF signal input and a peak output in communication with the RF signal input. Further included is main neutralization circuitry having a main neutralization input in communication with the peak input and a main neutralization output in communication with the main input, wherein the main neutralization circuitry is configured to inject a main neutralization signal into the main input such that the main neutralization signal is 180°±10% out of phase and equal in amplitude to within ±10% of a main parasitic feedback signal passed from the main output to the main input by way of a main parasitic feedback capacitance.

An LNA having a plurality of paths, each of which can be controlled independently to achieve a gain mode. Each path includes at least an input FET and an output FET coupled in series. A gate of the output FET is controlled to set the gain of the LNA. Signals to be amplified are applied to the gate of the input FET. Additional stacked FETs are provided in series between the input FET and the output FET.

An LNA having a plurality of paths, each of which can be controlled independently to achieve a gain mode. Each path includes at least an input FET and an output FET coupled in series. A gate of the output FET is controlled to set the gain of the LNA. Signals to be amplified are applied to the gate of the input FET. Additional stacked FETs are provided in series between the input FET and the output FET.

A multistage amplifier includes: N amplifiers (N≥2), a (k+1).sup.th amplifier cascaded to a k.sup.th amplifier (1≤k≤N−1), and each amplifier being configured to amplify a multicarrier signal; and an extraction circuit including an input and an output, the input being connected to an output of a j.sup.th amplifier (1≤j≤N−1), and the output providing a compensation signal to an input of a (j+1).sup.th amplifier or an output of the (j+1).sup.th amplifier. The extraction circuit includes a filter circuit connected to the output of the j.sup.th amplifier that extracts a distortion frequency component of n times a differential frequency f2−f1 (n≥1), a phase shifter cascaded to the filter circuit that shifts a phase of the component, and a gain adjustment circuit cascaded to the phase shifter that adjusts an amplitude of the component and generates the compensation signal.

A multistage amplifier includes: N amplifiers (N≥2), a (k+1).sup.th amplifier cascaded to a k.sup.th amplifier (1≤k≤N−1), and each amplifier being configured to amplify a multicarrier signal; and an extraction circuit including an input and an output, the input being connected to an output of a j.sup.th amplifier (1≤j≤N−1), and the output providing a compensation signal to an input of a (j+1).sup.th amplifier or an output of the (j+1).sup.th amplifier. The extraction circuit includes a filter circuit connected to the output of the j.sup.th amplifier that extracts a distortion frequency component of n times a differential frequency f2−f1 (n≥1), a phase shifter cascaded to the filter circuit that shifts a phase of the component, and a gain adjustment circuit cascaded to the phase shifter that adjusts an amplitude of the component and generates the compensation signal.