A device includes an integrated circuit (IC) die. The IC die includes a silicon germanium (SiGe) substrate, a first RF signal input terminal, a first RF signal output terminal, a first amplification path between the first RF signal input terminal and the first RF signal output terminal, a second RF signal input terminal, a second RF signal output terminal, and a second amplification path between the second RF signal input terminal and the second RF signal output terminal. The device includes a first power transistor die including a first input terminal electrically connected to the first RF signal output terminal and a second power transistor die including a second input terminal electrically connected to the second RF signal output terminal. The first amplification path can include two heterojunction bipolar transistors (HBTs) connected in a cascode configuration and the second amplification path can include two HBTs connected in a cascode configuration.

A system and method for multi-band digital pre-distortion (DPD) for a non-linear system. The system includes a DPD circuitry configured to perform multi-band DPD on a multi-band input signal to compensate for a non-linearity of a non-linear system. The multi-band input signal includes input signals of multiple frequency bands and the DPD circuitry is configured to perform DPD on an input signal of each frequency band per frequency band. The DPD circuitry is configured to perform the DPD using a combination of a look-up table (LUT) that evaluates a non-linear function and computation of terms of a non-linear polynomial of one or more variables representing the input signals of multiple frequency bands. Both the non-linear function and the non-linear polynomial are in a reduced dimension lower than a dimension of the multi-band input signal.

A system and method for digital correction for a dynamically varying non-linear system. The system includes a correction circuitry including at least one look-up table (LUT). The correction circuitry is configured to receive an input signal and modify the input signal to be processed by the non-linear system using at least one LUT to correct non-linearity incurred by the non-linear system. The at least one LUT is addressed by a magnitude or power of the input signal and a dynamically varying parameter associated with the input signal. The dynamically varying parameter may be one of average signal power of the input signal, a differential of the average power of the input signal, a directional beam index, or temperature.

Amplifier circuits, radio communication circuits, radio communication devices, and methods provided in this disclosure. The amplifier circuit may include an amplifier configured to amplify an input signal to provide an output signal. The output signal of the amplifier may include a direct current (DC) signal. The amplifier circuit may further include a current source coupled to the amplifier. The current source may be configured to receive an electrical supply. The current source may further be configured to divide the direct current (DC) signal of the output signal based on the electrical supply.

Amplifier circuits, radio communication circuits, radio communication devices, and methods provided in this disclosure. The amplifier circuit may include an amplifier configured to amplify an input signal to provide an output signal. The output signal of the amplifier may include a direct current (DC) signal. The amplifier circuit may further include a current source coupled to the amplifier. The current source may be configured to receive an electrical supply. The current source may further be configured to divide the direct current (DC) signal of the output signal based on the electrical supply.

Various embodiments provide systems, devices, and methods for a multi-core digital power amplifier with an unbalanced power combiner. In one example, two or more cores are combined with a transformer section that has a first coupling coefficient and another two or more cores are combined with a second transformer section that has a second coupling coefficient that is different than the first coupling coefficient. The outputs of different cores may be cross-coupled with the primary inductors of the transformers. The digital power amplifier may provide an output power that is flat over a relatively wide operating range. Other embodiments may be described and claimed.

An integrated circuit includes a passive component having a first metal feature and a second metal feature, the first metal feature and the second metal feature defining an interior area therebetween. The integrated circuit also includes set of spaced metal fill lines extending across the interior area and oriented to carry current orthogonal to current carried by the first metal feature and second metal feature.

An integrated circuit includes a passive component having a first metal feature and a second metal feature, the first metal feature and the second metal feature defining an interior area therebetween. The integrated circuit also includes set of spaced metal fill lines extending across the interior area and oriented to carry current orthogonal to current carried by the first metal feature and second metal feature.

Adaptive bias networks include small transistors connected to adjust gate bias voltage of one or more transistors of an amplifier or amplifier stage, or in a main or auxiliary path of a compound amplifier such as a Doherty amplifier. The small transistors are sized to avoid additional loading of the input. The adaptive bias circuits of preferred embodiments adjust the gate bias to produce a boost in gate bias voltage of an nFET transistor when the input power is in an upper portion of the amplifier or amplifier stage's input power range, thereby increasing the gain, and reduce gate bias voltage of a pFET transistor in the upper portion of the amplifier's input power range, thereby also increasing the gain. The adaptive bias networks can be implemented with varactors to vary DC voltage across the varactor to change its capacitance and compensate changing input capacitance of the amplifier input FET.

Adaptive bias networks include small transistors connected to adjust gate bias voltage of one or more transistors of an amplifier or amplifier stage, or in a main or auxiliary path of a compound amplifier such as a Doherty amplifier. The small transistors are sized to avoid additional loading of the input. The adaptive bias circuits of preferred embodiments adjust the gate bias to produce a boost in gate bias voltage of an nFET transistor when the input power is in an upper portion of the amplifier or amplifier stage's input power range, thereby increasing the gain, and reduce gate bias voltage of a pFET transistor in the upper portion of the amplifier's input power range, thereby also increasing the gain. The adaptive bias networks can be implemented with varactors to vary DC voltage across the varactor to change its capacitance and compensate changing input capacitance of the amplifier input FET.