An integrated circuit architecture and circuitry is defined by a die structure with a plurality of exposed conductive pads arranged in a grid of rows and columns. The die structure has a first operating frequency region with a first transmit and receive chain, and a second operating frequency region with a second transmit chain and a second receive chain. There is a shared region of the die structure defined by an overlapping segment of the first operating frequency region and the second operating frequency region with a shared power supply input conductive pad connected to the first transmit chain, the second transmit chain, the first receive chain, and the second receive chain, and a shared power detection output conductive pad connected to the first transmit chain and the second transmit chain.

A high frequency signal amplifying circuitry of an embodiment includes a first splitter, a first amplifier, a second amplifier, a loop oscillation suppressor, and a combiner. The first amplifier includes a second splitter, a first carrier amplifier, a first peak amplifier, and a first combiner. The second amplifier includes a third splitter, a second carrier amplifier, a second peak amplifier, and a second combiner. The second carrier amplifier being adjacent to an associated the first carrier amplifier or the second peak amplifier being adjacent to an associated the first peak amplifier. The loop oscillation suppressor located between the second carrier amplifier and the associated first carrier amplifier or the second peak amplifier and the associated first peak amplifier.

A high frequency signal amplifying circuitry of an embodiment includes a first splitter, a first amplifier, a second amplifier, a loop oscillation suppressor, and a combiner. The first amplifier includes a second splitter, a first carrier amplifier, a first peak amplifier, and a first combiner. The second amplifier includes a third splitter, a second carrier amplifier, a second peak amplifier, and a second combiner. The second carrier amplifier being adjacent to an associated the first carrier amplifier or the second peak amplifier being adjacent to an associated the first peak amplifier. The loop oscillation suppressor located between the second carrier amplifier and the associated first carrier amplifier or the second peak amplifier and the associated first peak amplifier.

In various embodiments, a semiconductor package includes a carrier amplifier connected to a first output of a power divider, and a first output matching network connected to the carrier amplifier and an output combining node. The first output matching network exhibits a phase delay during operation of the carrier amplifier. The semiconductor package includes a phase advance network connected to the first output matching network. The phase advance network is configured to offset at least a portion of the phase delay of the first output matching network. The semiconductor package includes a peaking amplifier connected to a second output of the power divider and the output combining node, and a second output matching network connected to the peaking amplifier.

In various embodiments, a semiconductor package includes a carrier amplifier connected to a first output of a power divider, and a first output matching network connected to the carrier amplifier and an output combining node. The first output matching network exhibits a phase delay during operation of the carrier amplifier. The semiconductor package includes a phase advance network connected to the first output matching network. The phase advance network is configured to offset at least a portion of the phase delay of the first output matching network. The semiconductor package includes a peaking amplifier connected to a second output of the power divider and the output combining node, and a second output matching network connected to the peaking amplifier.

The present invention relates to an amplifying device and to an amplifying system comprising the same. According to the present invention, an amplifier line-up is presented comprising four amplifying units which is operable in a Doherty mode and an outphasing mode. By integration of Chireix compensating elements in the matching networks used in the amplifying units a bandwidth improvement can be obtained.

The present invention relates to an amplifying device and to an amplifying system comprising the same. According to the present invention, an amplifier line-up is presented comprising four amplifying units which is operable in a Doherty mode and an outphasing mode. By integration of Chireix compensating elements in the matching networks used in the amplifying units a bandwidth improvement can be obtained.

In an acoustic wave device, a piezoelectric body is directly or indirectly laminated on a silicon support substrate, and a functional electrode is provided on the piezoelectric body. A support layer is directly or indirectly laminated on the silicon support substrate, and the support layer is located outside the functional electrode when viewed in plan view. A silicon cover layer is provided on the support layer that includes an insulating material, and a space A is defined by the silicon support substrate, the support layer, and the silicon cover layer. The electric resistance of the silicon support substrate is higher than the electric resistance of the silicon cover layer.

An acoustic wave device that includes a spinel layer, a piezoelectric layer, a temperature compensating layer between the spinel layer and the piezoelectric layer and an interdigital transducer electrode on the piezoelectric layer is disclosed. The piezoelectric layer is disposed between the interdigital transducer electrode and the spinel layer. The acoustic wave device is configured to generate an acoustic wave having a wavelength of λ. The piezoelectric layer can have a thickness that is less than λ. In some embodiments, the spinel layer can be a polycrystalline spinel layer.

Cascode amplifier having feedback circuits. In some embodiments, an amplifier can include a first transistor and a second transistor arranged in a cascode configuration, with each transistor having a gate. The amplifier can further include a first feedback circuit implemented between an output of the second transistor and the gate of the second transistor. The amplifier can further include a second feedback circuit implemented between the output of the second transistor and the gate of the first transistor.