An amplification circuit includes a first group of amplifiers including N first amplifiers, a second group of amplifiers including K second amplifiers, a first terminal, a second terminal, and a third terminal. Each of the N first amplifiers and each of the K second amplifiers includes an output. The second group of amplifiers is divided into a first subassembly of amplifiers and a second subassembly of amplifiers. The first subassembly includes M second amplifiers of the second group. The second subassembly includes K-M remaining second amplifiers of the second group. The first terminal is coupled to each output of the N first amplifiers and to a first radio frequency output terminal. The second terminal is coupled to each output of the M second amplifiers. The third terminal is coupled to each output of the K-M second remaining amplifiers and to a second radio frequency output terminal.

A wideband polar modulation transmitter includes a power amplifier (PA), a PA driver, a dynamic power supply (DPS), a PA driver V.sub.H controller, and a phase modulator. The phase modulator modulates a radio frequency (RF) carrier by an input phase modulating signal PM(t) to produce a phase modulated RF carrier. Meanwhile, the DPS produces a DPS voltage for the PA that follows an input amplitude modulating signal AM(t). Using the phase modulated RF carrier, the PA driver generates a PA drive signal V.sub.DRV for driving the PA. The PA drive signal V.sub.DRV has a high drive level V.sub.H and a low drive level V.sub.L. The PA driver V.sub.H controller is configured to control the magnitude of the high drive level V.sub.H so that it remains sufficiently high to force the PA to operate in a compressed mode (C-mode) most of the time but lowers the high drive level V.sub.H to force the PA to operate in a product mode (P-mode) during times low-magnitude events occur in the DPS voltage.

Described herein are systems and methods that manage polarization in coherent optical receivers by using analog signal processing that eliminates the need for ultra-fast, power-hungry ADCs and DSPs and that would require digitization of the full-bandwidth signal path and result in bulky and expensive circuit designs. Various embodiments of the invention provide polarization correction by using an analog polarization correction circuit that implements the equivalent of two matrix operations. This is accomplished by using analog electronics that comprises a combination of variable and unity gain amplifiers to align polarizations of input signals to generate a polarization-corrected output signal that is further aligned with the polarization frame of reference of the receiver.

A distributed power amplifier includes radio frequency (RF) input and output terminals. A first field effect transistor (FET) is coupled at a first gate terminal to the RF input terminal and at a first drain terminal to the RF output terminal. The first FET has a first periphery and a first source terminal electrically connected to ground potential. A second FET has a second periphery smaller than the first periphery. The second FET has a second gate terminal electrically coupled to the first gate terminal through a first inductor, a second drain terminal electrically coupled to the first drain terminal through a second inductor, and a second source terminal electrically connected to the ground potential. A drain voltage terminal, which excludes a resistive element, is electrically coupled to a drain bias network through which a drain bias voltage is applied to the first drain terminal and the second drain terminal.

A power amplifier system which operates at a narrow band with high power and high efficiency or at a wide band is provided. Said power amplifier system comprises at least one high power amplifier; at least one connection line; at least one input block which receives at least one signal from an input, which is connected to said high power amplifier and connection line, which sends received signal to either high power amplifier or connection line and which amplifies the power of the signal sent to the connection line; and at least one high power asymmetric output switch, which is connected to said high power amplifier and connection line and which sends signals coming from said high power amplifier and connection line to an output.

Included is a compensation circuit (9) having one end connected to another end of a first output circuit (7) and another end of a second output circuit (8) and another end grounded, the compensation circuit having an electrical length of 90 degrees at a first operation frequency and an electrical length of 45 degrees at a second operation frequency which is half of the first operation frequency.

The present disclosure in some embodiments relates to a method of calibrating a power amplifier performance and an apparatus therefor, which provide an optimal calibration of the output characteristics of a power amplifier to all possible combinations in the input signal source by enabling individualized calibrations for changes in the output characteristics at room temperature and changing temperatures, thereby improving the performance of the power amplifier.

Provided is a power amplification circuit that includes: a first transistor that has an emitter to which a first radio frequency signal is supplied, a base to which a first DC control current or DC control voltage is supplied and a collector that outputs a first output signal that corresponds to the first radio frequency signal; a first amplifier that amplifies the first output signal and outputs a first amplified signal; and a first control circuit that supplies the first DC control current or DC control voltage to the base of the first transistor in order to control output of the first output signal.

The present invention includes a first semiconductor chip, a second semiconductor chip, a first inductor, a second inductor, a second capacitor, protective diodes, and a third inductor. A field effect transistor includes a gate terminal, a drain terminal, and a source terminal connected to a ground terminal. The second semiconductor chip includes an input terminal and an output terminal connected in a direct current manner, and includes a first capacitor connected to the input terminal and to the ground terminal. The first inductor is connected between the output terminal and the gate terminal. The second inductor includes a first terminal connected to the input terminal. The second capacitor is connected between a second terminal of the second inductor and the ground terminal. Protective diodes are connected in series in a forward direction, and each has a cathode, and an anode connected to the ground terminal. The third inductor is connected between the cathode and the second terminal.

Diversity receiver front end systems with fixed impedance matching circuits to improve signal processing. The fixed impedance matching circuits can be configured to reduce out-of-band metrics such as noise figure and/or gain for a plurality of out-of-band frequency bands while reducing or not increasing above a certain threshold an in-band metric for the associated in-band frequency band. Each of a plurality of paths through the front-end systems can include fixed impedance matching circuits that accomplish this tuning to improve performance for the front-end systems.