A digital amplifier includes a pulse-width adjustment circuit that adjusts the pulse width of a digital signal, a switching circuit that amplifies the output signal of the pulse-width adjustment circuit, and a feedback signal generator that generates a feedback signal based on the output signal of the switching circuit.

An operational amplifier includes an output node; an output stage, comprising a plurality of output current paths and a plurality of control nodes, wherein the plurality of control nodes are respectively coupled to the plurality of output current paths, and the plurality of output current paths are coupled to the output node and respectively coupled to a plurality of power supply sources providing different voltages; and a selecting unit, configured to couple an internal output node of the operational amplifier to one of the plurality of control nodes of the output stage.

An LNA having a plurality of paths, each of which can be controlled independently to achieve a gain mode. Each path includes at least an input FET and an output FET coupled in series. A gate of the output FET is controlled to set the gain of the LNA. Signals to be amplified are applied to the gate of the input FET. Additional stacked FETs are provided in series between the input FET and the output FET.

The addition of gate bias resistors substantially balances the voltage across any number of series-connected FETs, while the feedback control of the gate-source voltage of one FET controls the current through all of the FETs. In this way, the thermal load and voltage stress are substantially balanced for series connected FETs operating in active linear mode (partially on), enabling operation at voltages much higher than the individual ratings of low cost, readily available FETs. Alternatively, series-connecting FETs for active-mode operation is thermally equivalent to paralleling because the FET heat load is practically uniform, enabling operation at much higher current. This concept is extended to a series connection of FETs that can block, pass, and/or limit alternating load current with the voltage applied across all the FETs being either polarity or alternating polarity. We provide analysis, practical design considerations, and simulation results.

A generator including a power combiner is provided. The power combiner includes a plurality of inputs, each input connectable to a respective power amplifier for receiving a respective power signal. A plurality of impedance matching circuit branches is connected to a respective one of the plurality of inputs. Each impedance matching circuit branch includes at least one high pass filter section and at least one low pass filter section through which the respective power signal passes. The impedance matching circuit branches are connected so as to combine the power signals from each power amplifier. An output is provided for outputting the combined power signal.

A PA module includes: a multilayer substrate having a ground pattern layer connected to a ground of a power source; amplifier transistors disposed on the multilayer substrate; a bypass capacitor having one end connected to the collector of the amplifier transistor; a first wiring line connecting the emitter of the amplifier transistor and the ground pattern layer to each other; a second wiring line connecting the emitter of the amplifier transistor and the ground pattern layer to each other; a third wiring line connecting the other end of the bypass capacitor and the ground pattern layer to each other; and a fourth wiring line formed between the amplifier transistor and the ground pattern layer and between the bypass capacitor and the ground pattern layer and connecting the first wiring line and the third wiring line to each other.

An electronic switch for switching between signal outputs comprises a 6-way symmetric hybrid ring combiner. Each port within the 6-way symmetric hybrid ring combiner is positioned at /4 wavelength increments around a circumference of the 6-way symmetric hybrid ring combiner.

Techniques (implemented in circuit arrangements, methods, computer instructions) are disclosed which permit digital pre-distortion for amplifiers. A common signal source provides a common analog signal from a digital input signal; a plurality of amplifiers amplifies a split signal which is a split version of the common analog signal; a built-in test circuit is configured to provide distortion information associated to distortion affecting the amplifier. The common signal source implements a signal conditioner to perform, in a signal path of the digital input signal, a feed-forward pre-distortion of the digital input signal according to a pre-distortion relationship mapping the digital input signal onto a pre-distorted version. The signal conditioner is configured to adjust the pre-distortion relationship in dependence on the distortion information.

A circuit includes an amplifier and pre-distortion circuit. The amplifier amplifies a modulated signal. The signal pre-distortion circuit performs a feed-forward pre-distortion of the modulated signal in a signal path in which the amplifier resides. The signal pre-distortion circuit includes: i) an envelope detector configured operative to provide an envelope information describing an envelope of the modulated signal; and ii) a built-in test circuit that determines distortion information describing a distortion in the signal path caused by amplitude variations. The signal pre-distortion circuit performs the feed-forward pre-distortion of the modulated signal on the basis of the distortion information.

A circuit includes an amplifier to amplify an input signal and generate an output signal. The circuit also includes a tuning network to tune frequency response of the amplifier. The tuning network includes at least one tunable capacitor, which includes at least one micro-electro mechanical system (MEMS) capacitor. The amplifier could include a first die, the at least one MEMS capacitor could include a second die, and the first die and the second die could be integrated in a single package. The at least one MEMS capacitor could include a MEMS superstructure over a control structure, which is to control the MEMS superstructure and tune the capacitance of the at least one MEMS capacitor.