Patent classifications
H03F3/211
MILLIMETRE WAVE POWER AMPLIFIER AND A METHOD OF OPTIMISING SUCH A POWER AMPLIFIER
A millimetre (mm) wave power amplifier includes a plurality of amplifiers, each amplifier including an amplifying FET including a gate, drain and source. The mm wave power amplifier also includes an input port, an output port, a VDS port being connected to a VDS voltage source for setting the drain-source voltage of the FET, and a VGS port being connected to a VGS voltage source for setting the gate-source voltage of the FET. The output ports of the amplifiers are connected to a signal combiner and the input ports of the amplifiers are connected to a signal splitter. At least one of (a) at least two of the VGS ports are connected to different VGS voltage sources, and (b) at least two of the VDS ports are connected to different VDS voltage sources.
Envelope tracking amplifier apparatus incorporating single-wire peer-to-peer bus
An envelope tracking (ET) amplifier apparatus is provided. The ET amplifier apparatus includes an ET integrated circuit (ETIC) and a distributed ETIC (DETIC) coupled to a single-wire bus that correspond to a first bus access priority and a second bus access priority, respectively. The ETIC and the DETIC can contend for access to the single-wire bus by asserting a bus contention indication(s) when the single-wire bus is in a defined bus state configured to permit bus contention. In a non-limiting example, a winner for the single-wire bus is a peer device having a highest bus access priority between the ETIC and the DETIC. In this regard, each of the ETIC and the DETIC can have a chance to initiate communications over the single-wire bus, thus making it possible for the single-wire bus to function based on bidirectional peer-to-peer (P2P) bus architecture capable of supporting more application and/or deployment scenarios.
Amplifier with improved isolation
An amplifier comprises a common emitter stage coupled to a first and a second input, a common base stage coupled to the common emitter stage and to a first and a second output, and a cancellation path coupled to the common emitter stage and the common base stage and to the first and second outputs. The cancellation path generates a first cancellation signal that is 180 degrees out of phase with a first leakage signal at the first output and a second cancellation signal that is 180 degrees out of phase with a second leakage signal at the second output. The cancellation path comprises a first cancellation transistor coupled to the common emitter stage and the common base stage and to the first output and a second cancellation transistor coupled to the common emitter stage and the common base stage and to the second output.
Doherty amplifier with additional delay element
An amplifier includes two amplifier circuits and a power splitter. The power splitter splits a signal to be amplified and generates a phase displacement of 90° in the case of a rated frequency between resulting partial signals. In this context, the amplifier circuits each amplify one of the partial signals or respectively a signal derived from one of the partial signals. The amplifier additionally contains a first delay element, which is arranged between the power splitter and one of the amplifier circuits.
Sequential broadband doherty power amplifier with adjustable output power back-off
The invention relates to a sequential broadband Doherty power amplifier with adjustable output power back-off The sequential broadband Doherty power amplifier has at least one input (I.sub.1, I.sub.2; RF.sub.in) for receiving at least one broadband HF signal, wherein the broadband HF signal or broadband HF signals (RF.sub.in) have at least an average power level (carrier/average) and a peak envelope power level (peak), with the average power level and the peak envelope power level defining a crest factor, and a first amplifier branch for amplifying the input signal, with the first amplifier branch providing the amplification substantially for the low and at least the average power level, at least one second amplifier branch for amplifying the input signal, wherein the second amplifier branch substantially provides the amplification for the peak envelope power level, wherein the output of the first amplifier branch is connected via an impedance inverter (Z.sub.T) to the output of the second amplifier branch, the junction (CN) being connected to the load (Z.sub.0) in a substantially directly impedance-matched manner, wherein the first and the second amplifier branch each have a supply voltage, with at least one of the supply voltages being variable as a function of the crest factor of the signal to be amplified, and wherein the signal propagation delay through the at least two amplifier branches is substantially identical in the operating range.
High frequency power amplifier, high frequency front-end circuit, and radio communication device
A high frequency power amplifier includes a first high frequency amplifier, a final high frequency amplifier, and a tunable filter. The tunable filter is connected between the first high frequency amplifier and the final high frequency amplifier. The first high frequency amplifier and the final high frequency amplifier are each a multimode/multiband power amplifier. The tunable filter is regulated such that its pass band includes the frequency band of a transmission signal and its attenuation band includes the frequency band of a reception signal in a communication band used in transmission and reception. The pass band and the attenuation band are switched by the tunable filter in accordance with the communication band used in transmission and reception.
Power amplifier having staggered cascode layout for enhanced thermal ruggedness
Power amplifier having staggered cascode layout for enhanced thermal ruggedness. In some embodiments, a radio-frequency (RF) amplifier such as a power amplifier (PA) can be configured to receive and amplify an RF signal. The PA can include an array of cascoded devices connected electrically parallel between an input node and an output node. Each cascoded device can include a common emitter transistor and a common base transistor arranged in a cascode configuration. The array can be configured such that the common base transistors are positioned in a staggered orientation relative to each other.
AN AMPLIFIER CIRCUIT FOR A PARAMETRIC TRANSDUCER AND A RELATED AUDIO DEVICE
An amplifier circuit for a parametric transducer, comprising: a signal processor for processing an input signal into first and second signals; and at least a pair of output stages arranged to respectively receive the first and second signals for generating amplified first and second signals respectively, which are provided to operate the parametric transducer. The input, first and second signals are arranged with a substantially similar frequency to cause a switching frequency of the amplifier circuit to be matched to a carrier frequency of the parametric transducer. A related audio device is also disclosed.
RESISTOR ARRAY, OUTPUT BUFFER, AND MANUFACTURING METHOD FOR SEMICONDUCTOR DEVICE
A resistor array made of a semiconductor includes a plurality of resistor groups and a common line that electrically connects the M-th resistors of the plurality of resistor groups. Each resistor group includes first to M-th resistors connected in series, M being an integer of 2 or greater, and at least one short-circuit line, each short-circuiting at least one, but not all, of the M resistors.
MULTI-COMPONENT DIGITAL PREDISTORTION
Various examples are directed to systems and methods for operating a plurality of power amplifiers. A predistortion circuit may pre-distort an input signal according to a predistortion configuration to generate a pre-distorted signal for the plurality of power amplifiers. An adaption circuit may receive a first feedback signal from a first power amplifier of the plurality of power amplifiers and generate predistortion correlation data describing a correlation between parameters of a model describing the plurality of power amplifiers. The adaption circuit may receive a first feedback signal from a second power amplifier of the plurality of power amplifiers and update the predistortion correlation data to generate updated predistortion correlation data using the first feedback signal from the second power amplifier. The adaption circuit may also generate the predistortion configuration using the updated predistortion correlation data.