An input buffer circuit includes an input differential amplifier unit, a differential amplifier stage, and a buffer. The input differential amplifier unit has input terminals and at least one output terminal, wherein at least two of the input terminals of the input differential amplifier unit are configured to be capacitively coupled respectively so as to provide at least one pair of signal paths for a first input signal and a second input signal of a differential input signal. The differential amplifier stage, coupled to the input differential amplifier unit, has first and second differential input terminals, and a corresponding output terminal, wherein the first and second differential input terminals are capable of being coupled to the first input signal and the second input signal respectively. The buffer, coupled to the output terminal of the differential amplifier stage, is used for outputting an output single-ended signal.

A flash analog to digital converter includes a voltage generator circuit, an encoder circuit, and first and second double differential amplifier circuits. The voltage generator circuit generates reference voltages according to first and second voltages. The encoder circuit generates a digital signal corresponding to an input signal according to first signals. The first double differential amplifier circuit compares the input signal with a first reference voltage in the reference voltages, to generate a corresponding one of the first signals. The second double differential amplifier circuit compares the input signal with a second reference voltage in the reference voltages, to generate a corresponding one of the first signals. A difference between the first voltage and the first reference voltage is less than that between the first voltage and the second reference voltage, and the first and the second double differential amplifier circuits have different circuit architectures.

A device includes a first amplifier coupled to a first signal conduction path and a second amplifier coupled to a second signal conduction path. A first coupler is coupled to the first signal conduction path. The first coupler is configured to produce an output signal based on a first signal carried by the first signal conduction path. A delay element is configured to impose a phase delay on the output signal of the first coupler to generate a delayed output signal. The device includes a second coupler coupled to the second signal conduction path. The second coupler is connected to the delay element and configured to inject the delayed output signal into the second signal conduction path.

A dual-mode envelope tracking (ET) power management circuit is provided. An ET amplifier(s) in the dual-mode ET power management circuit is capable of supporting normal-power user equipment (NPUE) mode and high-power user equipment (HPUE) mode. In the NPUE mode, the ET amplifier(s) amplifies a radio frequency (RF) signal(s) to an NPUE voltage based on a supply voltage for transmission in an NPUE output power. In the HPUE mode, the ET amplifier(s) amplifies the RF signal(s) to an HPUE voltage higher than the NPUE voltage based on a boosted supply voltage higher than the supply voltage for transmission in an HPUE output power higher than the NPUE output power. The ET amplifier(s) maintains a constant load line between the NPUE mode and the HPUE mode. By maintaining the constant load line, it is possible to maintain efficiency of the ET amplifier(s) in both the NPUE mode and the HPUE mode.

Apparatus and methods for an improved-efficiency Doherty amplifier are described. The Doherty amplifier may include a two-stage peaking amplifier that transitions from an “off” state to an “on” state later and more rapidly than a single-stage peaking amplifier used in a conventional Doherty amplifier. The improved Doherty amplifier may operate at higher gain values than a conventional Doherty amplifier, with no appreciable reduction in signal bandwidth.

A power stabilization circuit including a first reference power supply, a second reference power supply, and a combiner circuit coupled to the first reference power supply and the second reference power supply. The first reference power supply is configured to receive a first control signal, generate a first reference signal based on the first control signal, and provide the first reference signal to a first output power supply. The second reference power supply is configured to receive a second control signal, generate a second reference signal based on the second control signal, and provide the second reference signal to a second output power supply. The combiner circuit is configured to generate a combined reference signal based on the first reference signal and the second reference signal and drive a reference load based on the combined reference signal.

A device includes an amplifier having a first path and a second path and a first variable attenuator connected to the first path. The device includes a controller coupled to the first variable attenuator. The controller is configured to determine a magnitude of an input signal to the amplifier. When the magnitude of the input signal is below a threshold, the controller is configured to set an attenuation of the first variable attenuator to a first attenuation value. When the magnitude of the input signal is above the threshold, the controller is configured to set the attenuation of the first variable attenuator to a second attenuation value. The second attenuation value is less than the first attenuation value.

A power supply circuit includes a power amplifier that receives a direct current (DC) voltage from a first power source. A control signal applied to the power amplifier causes the power amplifier to convert the DC voltage to an alternating current (AC) output signal. The AC output signal is applied to a transformer that includes a first winding, a second winding, and a third winding. The first winding receives the AC output signal and the second winding receives an output current that varies in accordance with the AC output signal to apply current to a load. A rectifier includes a plurality of diodes configured to rectify a voltage across the third winding and clamp the voltage at the load. Return power from the third winding may be returned to the first power source.

In various embodiments, a semiconductor package includes a carrier amplifier connected to a first output of a power divider, and a first output matching network connected to the carrier amplifier and an output combining node. The first output matching network exhibits a phase delay during operation of the carrier amplifier. The semiconductor package includes a phase advance network connected to the first output matching network. The phase advance network is configured to offset at least a portion of the phase delay of the first output matching network. The semiconductor package includes a peaking amplifier connected to a second output of the power divider and the output combining node, and a second output matching network connected to the peaking amplifier.

A power amplifying apparatus includes a radio frequency (RF) power amplifier, a supply modulating unit, a phase shifting unit, and an envelope shaping unit. The RF power amplifier receives an input RF signal and outputs an amplified RF signal. The supply modulating unit provides the RF power amplifier with a supply voltage which varies with an original envelope of the input RF signal. The phase shifting unit receives a control signal and shifts a phase of the input RF signal to be inputted to the RF power amplifier by a shift amount which varies with the control signal. The envelope shaping unit receives the original envelope and provides the phase shifting unit with the control signal which varies with the original envelope.