A power amplifier circuit includes a first amplifier transistor, a first nonlinear element, and a current control circuit. The first amplifier transistor has a base or a gate into which a first signal is input, a collector or a drain from which a signal resulting from amplification of the first signal is output, and an emitter or a source that is grounded. The first nonlinear element is connected between the collector or the drain of the first amplifier transistor and the base or the gate of the first amplifier transistor. The current control circuit is connected between the ground and the base or the gate of the first amplifier transistor and controls current flowing through the first nonlinear element.

A first sub-collector layer functions as an inflow path of a collector current that flows in a collector layer of a heterojunction bipolar transistor. A collector ballast resistor layer having a lower doping concentration than the first sub-collector layer is disposed between the collector layer and the first sub-collector layer.

An improved method of providing high burst power to audio amplifiers from limited power sources, using parallel power paths to increase system efficiency without need for a power path controller, thus utilizing a simplified circuit operation and maximizing average power available for both the amplifier and supporting circuitry.

Systems, methods, and apparatus for beam steering and switching are disclosed. In one or more examples, a method for operating a communication system comprises switching, at least one switch in a rearrangeable switch network, to control input levels to power amplifiers in a power distribution network. The method further comprises outputting, by the power amplifiers in the power distribution network, power to a plurality of antenna elements. Further, the method comprises steering and distributing power, by the antenna elements, in beams associated with each of the antenna elements according to a level of the power in each of the antenna elements.

A fast-switching power management circuit operable to prolong battery life is provided. The power management circuit includes a voltage circuit that can generate an output voltage for amplifying an analog signal in a number of time intervals and a pair of hybrid circuits each causing the output voltage to change in any of the time intervals. A control circuit is configured to activate any one of the hybrid circuits during a preceding one of the time intervals to cause the output voltage to change in an immediately succeeding one of the time intervals. By starting the output voltage change earlier in the preceding time interval, it is possible to complete the output voltage change within a switching window in the succeeding time interval while concurrently reducing rush current associated with the output voltage change, thus helping to prolong battery life in a device employing the power management circuit.

Broadband feedforward power amplifiers are disclosed herein. In certain embodiments, a broadband feedforward power amplifier includes a power amplifier electrically connected between a radio frequency (RF) input and an RF output, and a feedforward compensation circuit including a first amplifier electrically connected in parallel with the power amplifier, a load impedance, and a second amplifier electrically connected between the radio frequency input and the load impedance. The feedforward compensation circuit generates a compensation signal based on sensing an output of the first amplifier and an output of the second amplifier, and provides the compensation signal to the radio frequency output to thereby compensate the power amplifier for non-linearity.

A power amplifier circuit includes a power splitter, a first amplifier, a second amplifier, a third amplifier, a fourth amplifier, a first bias circuit, a first line connecting the first bias circuit and the first amplifier, and a second line connecting the first bias circuit and the third amplifier on the same semiconductor substrate, in which the first line and the second line are formed such that a voltage drop amount of the first bias voltage between the first bias circuit and the first amplifier is substantially equal to a voltage drop amount of the first bias voltage between the first bias circuit and the third amplifier.

A power amplification circuit including: a power splitter which splits an input signal into a first signal and a second signal; a first carrier amplifier which amplifies the first signal to output a first amplified signal; a first peak amplifier which amplifies the second signal when a power level of the second signal is larger than or equal to a predetermined power level to output a second amplified signal; and a combiner which combines the first amplified signal and the second amplified signal, in which the first carrier amplifier and the first peak amplifier are provided to a same semiconductor substrate.

Wideband power combiners and splitters are provided herein. In certain embodiments, a power combiner/splitter is implemented with a first coil connecting a first port and a second port, and a second coil connecting a third port and a fourth port. The first coil and the second coil are inductively coupled to one another. For example, the first coil and the second coil can be formed using adjacent conductive layers of a semiconductor chip, an integrated passive device, or a laminate. The power combiner/splitter further includes a fifth port tapping a center of the first coil and a sixth port tapping a center of the second coil. The fifth port and the sixth port serve to connect capacitors and/or other impedance to the center of the coils to thereby provide wideband operation.

A distributed power amplifier includes radio frequency (RF) input and output terminals. A first field effect transistor (FET) is coupled at a first gate terminal to the RF input terminal and at a first drain terminal to the RF output terminal. The first FET has a first periphery and a first source terminal electrically connected to ground potential. A second FET has a second periphery smaller than the first periphery. The second FET has a second gate terminal electrically coupled to the first gate terminal through a first inductor, a second drain terminal electrically coupled to the first drain terminal through a second inductor, and a second source terminal electrically connected to the ground potential. A drain voltage terminal, which excludes a resistive element, is electrically coupled to a drain bias network through which a drain bias voltage is applied to the first drain terminal and the second drain terminal.