This application is generally related to methods and systems for improving amplifier performance. For example, the system includes two or more gain and phase modulators. The system also includes two or more component amplifiers operably coupled to, and downstream of, the power splitter, where each of the two or more component amplifiers is operably coupled to a respective one of the two or more gain and phase modulators. The system further includes a power combiner operably coupled to, and downstream of, the two or more component amplifiers, configured to output a power signal. The system even further includes a Walsh generator configured to generate and transmit first and second Walsh codes to each of the two or more gain and phase modulators. The first Walsh code is orthogonal to the second Walsh code. A first set of the first and second Walsh codes is inverted with respect to a second set of the first and second Walsh codes.

One example includes a device that is comprised of a pre-power amplifier, a power amplifier, a signal path, and a dynamic bias circuit. The pre-power amplifier amplifies an input signal and outputs a first amplified signal. The power amplifier receives the first amplified signal and amplifies the first amplified signal based on a dynamic bias signal to produce a second amplified signal at an output thereof. The signal path is coupled between an output of the pre-power amplifier and an input of the power amplifier. The dynamic bias circuit monitors the first amplified signal, generates the dynamic bias signal, and outputs the dynamic bias into the signal path.

An amplifier with stacked transconducting cells in parallel and/or cascade “current mode” combining is disclosed herein. In one or more embodiments, a method for operation of a high-voltage signal amplifier comprises inputting, into each transconducting cell of a plurality of transconducting cells, a direct current (DC) supply current (Idc), an alternating current (AC) radio frequency (RF) input current (I.sub.RF_IN), and an RF input signal (RF.sub.IN). The method further comprises outputting, by each of the transconducting cells of the plurality of transconducting cells, the DC supply current (Idc) and an AC RF output current (I.sub.RF_OUT). In one or more embodiments, the transconducting cells are connected together in cascode for the DC supply current (Idc), are connected together in parallel (or in cascade) for the RF input signal (RF.sub.IN), and are connected together in parallel (or in cascade) for the AC RF output currents (I.sub.RF_OUT).

In accordance with the embodiments of the present disclosure, a rack comprising a frame having first vertical posts on a first side and second vertical posts on a second side, between which a plurality of RF amplifier modules are mounted, is provided. The RF power outputs of the RF amplifier modules are connected to inputs of an RF power combiner to deliver a combined RF power output. The RF power combiner is arranged at least partially in at least one of a first volume between the first vertical posts of the frame or a second volume between the second vertical posts of the frame, thereby reducing a footprint of the rack.

Provided is a dual-mode power amplifier with switchable operating frequencies, comprising at least two preamplifier circuits, a matching circuit for matching an output signal of each preamplifier circuit, an input transformer T1 with at least two output taps, an output stage amplifier circuit with the same number as the output taps of the input transformer T1, an output transformer T2, a switch S1 and a switch S2; circuit power supply VCC1 is loaded on an input end of the input transformer T1 via switch S1 and switch S2 respectively; operating frequencies of the matching circuit are different. The power amplifier realizes the switching of the maximum output power, supports the signal amplification in more frequency bands, and solves the problems in the prior art that the number of components is too large because more groups of power amplifiers for power amplification are needed for different frequency bands.

A multiple-path amplifier (e.g., a Doherty amplifier) includes a semiconductor die, a radio frequency (RF) signal input terminal, a combining node structure integrally formed with the semiconductor die, and first and second amplifiers (e.g., main and peaking amplifiers) integrally formed with the die. Inputs of the first and second amplifiers are electrically coupled to the RF signal input terminal. A plurality of wirebonds is connected between an output of the first amplifier and the combining node structure. An output of the second amplifier is electrically coupled to the combining node structure (e.g., through a conductive path with a negligible phase delay). A phase delay between the outputs of the first and second amplifiers is substantially equal to 90 degrees. The second amplifier may be divided into two amplifier portions that are physically located on opposite sides of the first amplifier.

A power amplifier module includes a combining circuit including a combiner. The combining circuit further includes a first inductor connected in series between an output terminal of a first amplifier and the combiner, a second inductor connected in series between an output terminal of a second amplifier and the combiner, and a second capacitor having an end connected to the combiner and another end grounded. A phase of a third signal from the output terminal of the first amplifier to the second amplifier through the combiner is delayed by about 45 degrees in the first inductor and the second capacitor, and is delayed by about 45 degrees in the second inductor and the second capacitor. A phase of the third signal from the output terminal of the first amplifier to the second amplifier through the first capacitor is advanced by about 90 degrees.

A multi-mode envelope tracking (ET) amplifier circuit is provided. The multi-mode ET amplifier circuit can operate in a low-resource block (RB) mode, a mid-RB mode, and a high-RB mode. The multi-mode ET amplifier circuit includes fast switcher circuitry having a first switcher path and a second switcher path and configured to generate an alternating current (AC) current. A control circuit activates the fast switcher circuitry in the mid-RB mode and the high-RB mode, while deactivating the fast switcher circuitry in the low-RB mode. More specifically, the control circuit selectively activates one of the first switcher path and the second switcher path in the mid-RB mode and activates both the first switcher path and the second switcher path in the high-RB mode. As a result, it is possible to improve efficiency of ET tracker circuitry and the multi-mode ET amplifier circuit in all operation modes.

A power amplifier includes initial-stage and output-stage amplifier circuits, and initial-stage and output-stage bias circuits. The initial-stage amplifier circuit includes a first high electron mobility transistor having a source electrically connected to a reference potential, and a gate to which a radio-frequency input signal is inputted, and a first heterojunction bipolar transistor having an emitter electrically connected to a drain of the first high electron mobility transistor, a base electrically connected to the reference potential in an alternate-current fashion, and a collector to which direct-current power is supplied and from which a radio-frequency signal is outputted. The output-stage amplifier circuit includes a second heterojunction bipolar transistor having an emitter electrically connected to the reference potential, a base to which the radio-frequency signal outputted from the first heterojunction bipolar transistor is inputted, and a collector to which direct-current power is supplied and from which a radio-frequency output signal is outputted.

An amplifier includes: a first transistor chip including a plurality of cells and provided beside an input matching substrate; a second transistor chip including a plurality of cells and provided beside the input matching substrate; a plurality of first bonding wires connecting the input matching substrate and the first transistor chip; and a plurality of second bonding wires connecting the input matching substrate and the second transistor chip, and variance of the mutual inductance of the first bonding wires and the second bonding wires is compensated by adjusting the self-inductance of the first bonding wires and the second bonding wires.