According to one embodiment, an amplifier circuit includes N (N>=3) transistors, two first branches and N−2 second branches. The N (N>=3) transistors are connected in parallel. The two first branches each include the transistor and a first transmission line which is connected to an output terminal of the transistor. The N−2 second branches each include the transistor and a second transmission line which is connected to the output terminal of the transistor. For each of the first branches, a sum between an electrical length of a parasitic component of the transistor and the electrical length of the first transmission line are odd multiples of approximately 90 degrees. For each of the second branches, the sum between the electrical length of the parasitic component of the transistor and the electrical length of the second transmission line are multiples of approximately 180 degrees.

A mixer includes a load portion connected between an input terminal of a first power voltage and an output terminal of the radio frequency transmit signal and configured to adjust a magnitude of the radio frequency transmit signal, a first switching unit connected to an output terminal of the radio frequency transmit signal, and configured to perform a first switching operation in response to a plurality of local oscillation signals, and a second switching unit connected between the first switching unit and an input terminal of a second power voltage, lower than the first power voltage, and configured to perform a second switching operation in response to a plurality of baseband signals, the plurality of local oscillation signals include an I+ baseband signal, an I baseband signal, a Q+ baseband signal, and a Q baseband signal, and the second switching unit includes a first branch performing a switching operation under control of the I+ baseband signal and the Q+ baseband signal, a second branch performing a switching operation under control of the I baseband signal and the Q baseband signal, a third branch performing a switching operation under control of the Q+ baseband signal and the I baseband signal, and a fourth branch performing a switching operation under control of the Q baseband signal and the I+ baseband signal.

A line driver circuit includes a first input terminal, a second input terminal, a first input stage, a second input stage, a first output stage, and a second output stage. The first input stage includes a first input coupled to the first input terminal, and a second input coupled to the second input terminal. The second input stage includes a first input coupled to the first input terminal, and a second input coupled to the second input terminal. The first output stage includes a first input coupled to a first output terminal of the first input stage and a second input coupled to a first output terminal of the first input stage. A second output stage includes a first input coupled to a second output terminal of the first input stage and a second input coupled to a second output terminal of the first input stage.

Herein disclosed in some embodiments is a fault detector for power amplifiers of a communication system. The fault detector can detect a portion of the power amplifiers that are in fault condition and can prevent or limit current flow to the power amplifiers in fault condition while allowing the rest of the power amplifiers to operate normally. The fault detector can further indicate which power amplifiers are in fault condition and/or the cause for the power amplifiers to be in fault condition. Based on the indication, a controller can direct communications away from the power amplifiers in fault condition and/or perform operations to correct the fault condition.

The disclosure provides an amplifying apparatus including a plurality of amplifying circuits and an adjusting circuit. The input terminals of the amplifying circuits are coupled to a first common node. The output terminals of the amplifying circuits are coupled to a second common node. The adjusting circuit adjusts an input signal to generate an adjusted signal to the first common node; the adjusting circuit adjusts the signal of the second common node; or the adjusting circuit adjusts the input signal to generate the adjusted signal to the first common node and adjusts the signal of the second common node. The first control signal and the second control signal respectively control the amplifying circuits and the adjusting circuit to determine the gain, the linear power, and the output current of the amplifying apparatus.

A multi-stage amplifier including a pre-driver stage, and method of operating the same. In one example, the amplifier includes an output stage with a first output transistor coupled to an oppositely doped second output transistor and to an output terminal. The pre-driver stage includes with a first driver transistor coupled to the first output transistor, and a second driver transistor coupled to the second output transistor. The pre-driver stage also includes a first current mirror and a second current mirror coupled to the first driver transistor and the second driver transistor. The pre-driver stage also includes a first translinear loop having a first translinear loop transistor and a second translinear loop having a second translinear loop transistor coupled to the first output transistor and the second output transistor.

A testing system includes: a signal generator arranged to generate a testing signal; a dividing circuit coupled to the signal generator for providing a plurality of input signals according to the testing signal; and a plurality of power-amplifier chips coupled to the dividing circuit for being tested by generating a plurality of output signals for a predetermined testing time according to the plurality of input signals respectively.

A power amplifier and power amplification circuit are described herein. An illustrative power amplifier is disclosed to include an input terminal, a drive amplifier connected to the input terminal, and an impedance modulator having a capacitance that is adjusted inversely and proportionately relative to a signal output by the drive amplifier, wherein the impedance modulator provides a feedback loop between an output of the drive amplifier and the input terminal.

A digital power amplifier comprising at least two individually activatable amplifiers connected to an output network comprising a first hybrid coupler. An output of a first amplifier is connected to a first input of the first hybrid coupler and an output of a second amplifier is connected to a second input of the first hybrid coupler such that activating an amplifier of the at least two amplifiers causes the amplifier to load modulate another activated amplifier of at least two amplifiers.

A power amplifier circuit includes a first power supply terminal electrically connected to a first power amplifier; a second power supply terminal electrically connected to a second power amplifier subsequent to the first power amplifier; a first external power supply line configured to electrically connect a power supply circuit configured to output a power supply potential corresponding to an amplitude level of a high-frequency input signal and the first power supply terminal; and a second external power supply line configured to electrically connect the power supply circuit and the second power supply terminal. An inductance value of the first external power supply line is higher than an inductance value of the second external power supply line.