A radio-frequency integrated chip (RFIC) is described which provides a number of low noise amplifiers (LNAs) and load circuits. The low noise amplifiers are organized in groups. In some embodiments, a load circuit may be dedicated to a group or shared between groups. The RFIC includes an LNA group including a plurality of LNAs configured to amplify carrier signals related to a plurality of frequency bands, a second LNA group configured to amplify a plurality of second carrier signals, a first load circuit group dedicated to the first LNA group, a second load circuit group dedicated to the second LNA group, and a third load circuit group shared between the first LNA group and the second LNA group. In some embodiments the third load circuit group adaptively performs frequency down-conversion on a carrier signal amplified by at least one of the first LNA group and the second LNA group.

An embodiment of a dual-path amplifier includes a power splitter connected to first and second power amplifiers respectively connected to first and second transmission lines connected to a power combiner having a phase-offset deficit at the second harmonic frequency 2f0, where the first and second transmission lines are designed to provide a complementary phase offset at 2f0 substantially equal to the phase-offset deficit such that the two amplified signals will be combined at the power converter with a total phase offset at 2f0 of about 180 degrees in order to reduce harmonic distortion in the amplified output signal, without substantially diminishing the output power at the fundamental frequency f0. In certain PCB-based implementations, the transmission lines include metal traces and lumped elements providing different impedance transformations that achieve the complementary phase offset, where the metal traces may have significantly different physical and electrical characteristics.

An integrated transformer arrangement for combining output signals of multiple differential power amplifiers to a single-ended load. The integrated transformer arrangement comprises a first transformer branch comprising an inductor loop. The inductor loop comprises a set of N windings connected in series. The first transformer branch further comprises a number of primary inductors. Each primary inductor comprises a winding placed concentrically to one winding of the inductor loop, and each primary inductor is configured to couple to a differential output of one of the multiple differential power amplifiers. The integrated transformer arrangement further comprises a secondary inductor comprising a winding placed concentrically to a winding of the inductor loop, and the secondary inductor is configured to couple to the single-ended load.

An active balun circuit includes first and second transistors having emitters electrically coupled to each other and configured to output differential signals and a circuit element coupled between the connection point of the emitter of the first transistor and the emitter of the second transistor and a reference potential. The impedance of the circuit element at a particular frequency of the input signal appears significantly larger than impedances at other frequencies. An input signal from an input terminal is inputted to the base of the first transistor. The reference potential is applied to the base of the second transistor. A supply voltage is applied to the collector of the first transistor and the collector of the second transistor. A signal from the collector of the first transistor and a signal from the collector of the second transistor are outputted as the differential signals.

A Doherty amplifier includes a distributor, a first amplifier, a second amplifier, a third node, an impedance conversion circuit having a first end connected to a first node and a second end connected to the third node, and rotating an impedance viewed from the first amplifier to the third node with respect to an impedance viewed from the first amplifier to the first node within a range of 36045 on a Smith chart in a second harmonic wave, and a harmonic tuning circuit having a third end connected to a line connecting the first amplifier and the third node at the first node, and making an absolute value of an impedance with respect to a reference potential at the third end in the second harmonic wave smaller than an absolute value of an impedance with respect to the reference potential at the third end in the fundamental wave.

This disclosure is directed to reducing output voltage distortions of Variable Gain Amplifiers (VGAs). A VGA may include a number of amplifiers each providing a portion of a total gain of the VGA. For example, a processing circuit may select one or more of the amplifiers of the VGA to provide the output signal with a selected gain. However, the selected amplifiers may provide amplified signals with one or more distortion signals when receiving a bias voltage. Systems and methods are described to reduce or cancel the distortion signals of the selected amplifiers by providing a subthreshold nonzero bias voltage (e.g., a weak voltage) to the remaining (e.g., non-selected) amplifiers of the VGA. For example, the non-selected amplifiers may receive the weak voltage to provide distortion signals with similar voltage amplitude and out of phase compared to the distortion signals of the selected amplifiers.

An outphasing amplifier includes a first amplifier, a second amplifier, a first coupler coupling a first signal and a third signal, a second coupler coupling a second signal and a fourth signal, a first impedance converter inputting the first signal coupled with the third signal, a second impedance converter inputting the second signal coupled with the fourth signal, a combiner combining the first and the second signals output from the first and the second impedance converters and outputting an output signal, and a signal processor outputting the first signal having a first phase to the first amplifier, outputting the second signal having a second phase to the second amplifier, outputting the third signal having at least one of a third phase and a first amplitude to the first coupler, and outputting the fourth signal having at least one of a fourth phase and a second amplitude to the second coupler.

A scalable periphery tunable matching power amplifier is presented. Varying power levels can be accommodated by selectively activating or deactivating unit cells of which the scalable periphery tunable matching power amplifier is comprised. Tunable matching allows individual unit cells to see a constant output impedance, reducing need for transforming a low impedance up to a system impedance and attendant power loss. The scalable periphery tunable matching power amplifier can also be tuned for different operating conditions such as different frequencies of operation or different modes.

An apparatus for detecting difference in operating characteristics of a main circuit by using a replica circuit is presented. In one exemplary case, a sensed difference in operating characteristics of the two circuits is used to drive a tuning control loop to minimize the sensed difference. In another exemplary case, several replica circuits of the main circuit are used, where each is isolated from one or more operating variables that affect the operating characteristic of the main circuit. Each replica circuit can be used for sensing a different operating characteristic, or, two replica circuits can be combined to sense a same operating characteristic.

A power amplification system with shared common base biasing is disclosed. A method for power amplification at a controller of a power amplification system comprising a plurality of cascode amplifier sections can include receiving a band select signal indicative of one or more frequency bands of a radio-frequency input signal to be amplified and transmitted. The method may further include biasing a common base stage of each of the plurality of cascode amplifier sections, and biasing a common emitter stage of a subset of the plurality of cascode amplifier sections.