In accordance with the embodiments of the present disclosure, a rack comprising a frame having first vertical posts on a first side and second vertical posts on a second side, between which a plurality of RF amplifier modules are mounted, is provided. The RF power outputs of the RF amplifier modules are connected to inputs of an RF power combiner to deliver a combined RF power output. The RF power combiner is arranged at least partially in at least one of a first volume between the first vertical posts of the frame or a second volume between the second vertical posts of the frame, thereby reducing a footprint of the rack.

A Doherty amplifier including a main amplifier and a peak amplifier is mounted on a package substrate. A low noise amplifier is further mounted on the package substrate. A transmit/receive switch switches in terms of time between a transmission connection state in which an output signal of the Doherty amplifier is supplied to an antenna and a reception connection state in which a signal received by the antenna is inputted to the low noise amplifier.

An RF module includes a switch IC having connection electrodes on a first main face and connection electrodes on a second main face; a mounting substrate which has a first mounting face at the first main face side and a second mounting face at the second main face side and in which the switch IC is mounted; signal lines for a band A, which are formed at the first mounting face side of the mounting substrate; signal lines for a band B, which are formed at the second mounting face side of the mounting substrate; a band A filter; and a band B filter. Among the band A filter and the band B filter, only the band A filter is mounted on the first mounting face and only the band B filter is mounted on the second mounting face.

A multi-stage amplifier with a high signal-to-noise ratio is introduced. Multiple amplification stages are cascaded between an input terminal and an output terminal of the amplifier. A controller switches the output stage among the multiple amplification stages from a normal mode to an attenuation mode in response to the amplifier input being lower than the threshold. In the attenuation mode, the output stage provides an attenuation resistor coupled in series with the load resistor of the amplifier. Noise is successfully attenuated by the attenuation-mode output stage.

A power supply consisting of double stages. Wherein one stage generates a high voltage using current methods. While the second stage generator an amperage pulse which is inserted into the high voltage circuit, causing both elements to fuse and operate as one entity.

A power amplifier circuit includes power amplifiers connected in stages to amplify a high-frequency input signal and to output an amplified high-frequency output signal, bias circuits each of which outputs a bias current to a corresponding one of the power amplifiers, and a bias control circuit configured to output a bias control current based on a second reference potential that varies in response to power of the high-frequency output signal and that is a potential of a portion in one bias circuit of the bias circuits to one or more bias circuits in a stage preceding the one bias circuit for increasing a bias current outputted from the one or more bias circuits in the stage preceding the one bias circuit.

Embodiments of the disclosure relate to optimizing power efficiency of a power amplifier circuit to reduce power consumption in a remote unit in a wireless distribution system (WDS). A power amplifier circuit is provided in the remote unit to amplify a received input signal associated with a signal channel(s) to generate an output signal at an aggregated peak power. In this regard, a control circuit is configured to analyze at least one physical property related to the signal channel(s) to determine a maximum output power of the power amplifier circuit. Accordingly, the control circuit configures the power amplifier circuit according to the determined maximum output power. By configuring the maximum output power based on the signal channel(s) in the input signal, it may be possible to optimize the power efficiency of the power amplifier circuit, thus helping to reduce the power consumption of the remote unit.

A PA module includes: a multilayer substrate having a ground pattern layer connected to a ground of a power source; amplifier transistors disposed on the multilayer substrate; a bypass capacitor having one end connected to the collector of the amplifier transistor; a first wiring line connecting the emitter of the amplifier transistor and the ground pattern layer to each other; a second wiring line connecting the emitter of the amplifier transistor and the ground pattern layer to each other; a third wiring line connecting the other end of the bypass capacitor and the ground pattern layer to each other; and a fourth wiring line formed between the amplifier transistor and the ground pattern layer and between the bypass capacitor and the ground pattern layer and connecting the first wiring line and the third wiring line to each other.

An LNA having a plurality of paths, each of which can be controlled independently to achieve a gain mode. Each path includes at least an input FET and an output FET coupled in series. A gate of the output FET is controlled to set the gain of the LNA. Signals to be amplified are applied to the gate of the input FET. Additional stacked FETs are provided in series between the input FET and the output FET.

A power amplifier includes a power splitter that splits a first signal into a second signal and a third signal, a first amplifier that amplifies the second signal within an area where the first signal has a power level greater than or equal to a first level and that outputs a fourth signal, a second amplifier that amplifies the third signal within an area where the first signal has a power level greater than or equal to a second level higher than the first level and that outputs a fifth signal, an output unit that outputs an amplified signal of the first signal, a first and a second LC parallel resonant circuit, and a choke inductor having an end to which a power supply voltage is supplied and another end connected to a node of the first and second LC parallel resonant circuits.