Systems and methods for amplifying a signal is described. A circuit may convert an input radio frequency (RF) signal into a first RF signal with power level matching a power capacity of a first transistor of a first size in a carrier amplifier stage, a second RF signal with power level matching a power capacity of a second transistor of the first size in a peaking amplifier stage, and a third RF signal with third power level matching a power capacity of a third transistor of a second size in another peaking amplifier stage. The circuit may amplify the first, second, and third RF signals to generate first, second, and third amplified RF signals, respectively. The circuit may combine the first, second, and third amplified RF signals, into an output RF signal that is an amplified version of the input RF signal.

A Doherty power amplifier circuit having a main power amplification device, an auxiliary power amplification device arranged in parallel with the main power amplification device, and a load modulation circuit comprising a harmonic injection circuit connected with respective outputs of the main power amplification device and the auxiliary power amplification device. The harmonic injection circuit is arranged to transfer harmonic components generated at the main power amplification device to the auxiliary power amplification device and harmonic components generated at the auxiliary power amplification device to the main power amplification device, when both the main and auxiliary power amplification devices are operating, for modulating the respective outputs of the main power amplification device and the auxiliary power amplification device.

A Doherty power amplifier circuit having a main power amplification device, an auxiliary power amplification device arranged in parallel with the main power amplification device, and a load modulation circuit comprising a harmonic injection circuit connected with respective outputs of the main power amplification device and the auxiliary power amplification device. The harmonic injection circuit is arranged to transfer harmonic components generated at the main power amplification device to the auxiliary power amplification device and harmonic components generated at the auxiliary power amplification device to the main power amplification device, when both the main and auxiliary power amplification devices are operating, for modulating the respective outputs of the main power amplification device and the auxiliary power amplification device.

A multi-voltage power generation circuit is disclosed. More specifically, the multi-voltage generation circuit includes multiple voltage modulation circuits that are configured to generate and maintain multiple modulated voltages. In a non-limiting example, the multiple modulated voltages can be used for amplifying multiple radio frequency (RF) signals concurrently. Contrary to using multiple direct-current (DC) to DC (DC-DC) converters for generating the multiple modulated voltages, the voltage modulation circuits are configured to share a single current modulation circuit based on time-division. By sharing a single current modulation circuit among the multiple voltage modulation circuits, it is possible to concurrently support multiple load circuits (e.g., power amplifier circuits) with significantly reduced footprint.

A multi-voltage power generation circuit is disclosed. More specifically, the multi-voltage generation circuit includes multiple voltage modulation circuits that are configured to generate and maintain multiple modulated voltages. In a non-limiting example, the multiple modulated voltages can be used for amplifying multiple radio frequency (RF) signals concurrently. Contrary to using multiple direct-current (DC) to DC (DC-DC) converters for generating the multiple modulated voltages, the voltage modulation circuits are configured to share a single current modulation circuit based on time-division. By sharing a single current modulation circuit among the multiple voltage modulation circuits, it is possible to concurrently support multiple load circuits (e.g., power amplifier circuits) with significantly reduced footprint.

an amplifier having an input terminal and an output terminal. The input terminal is configured to receive a radio frequency (RF) input signal. The device includes an output network coupled to the output terminal of the power amplifier and a first passively tunable integrated circuit (PTIC) coupled to the output network. The first PTIC includes a direct-current (DC) bias voltage input terminal configured to receive a fixed bias voltage, a control signal input terminal configured to receive a time-varying control signal, wherein the fixed bias voltage in combination with the time-varying control signal sets an operating reference point of the first PTIC, and an input terminal electrically connected to the output terminal of the amplifier, wherein a change in an output voltage signal generated by the power amplifier causes the first PTIC to modify a first effective impedance of a load presented to the power amplifier via the output network.

A system for sensing an electrical quantity may include a sensing stage configured to sense the electrical quantity and generate a sense signal indicative of the electrical quantity, wherein the electrical quantity is indicative of an electrical signal generated by a Class-DG amplifier configured to drive a load wherein the Class-DG amplifier has multiple signal-level common modes and a common-mode compensator configured to compensate for changes to a common-mode voltage of a differential supply voltage of the driver occurring when switching between signal-level common modes of the Class-DG amplifier.

Bias circuits and methods for silicon-based amplifier architectures that are tolerant of supply and bias voltage variations, bias current variations, and transistor stack height, and compensate for poor output resistance characteristics. Embodiments include power amplifiers and low-noise amplifiers that utilize a cascode reference circuit to bias the final stages of a cascode amplifier under the control of a closed loop bias control circuit. The closed loop bias control circuit ensures that the current in the cascode reference circuit is approximately equal to a selected multiple of a known current value by adjusting the gate bias voltage to the final stage of the cascode amplifier. The final current through the cascode amplifier is a multiple of the current in the cascode reference circuit, based on a device scaling factor representing the relative sizes of the transistor devices in the cascode amplifier and in the cascode reference circuit.

Bias circuits and methods for silicon-based amplifier architectures that are tolerant of supply and bias voltage variations, bias current variations, and transistor stack height, and compensate for poor output resistance characteristics. Embodiments include power amplifiers and low-noise amplifiers that utilize a cascode reference circuit to bias the final stages of a cascode amplifier under the control of a closed loop bias control circuit. The closed loop bias control circuit ensures that the current in the cascode reference circuit is approximately equal to a selected multiple of a known current value by adjusting the gate bias voltage to the final stage of the cascode amplifier. The final current through the cascode amplifier is a multiple of the current in the cascode reference circuit, based on a device scaling factor representing the relative sizes of the transistor devices in the cascode amplifier and in the cascode reference circuit.

The present disclosure provides an audio amplifying circuit and a playing device, including: N-order filters and an integrated circuit; after an original audio signal passes through the N-order filters, a filtered signal is obtained; after the filtered signal passes through the integrated circuit, a corresponding digital signal is output; where the number of operational amplifiers adopted in the N-order filters is smaller than N, and N is a natural number greater than 1.