A package that includes a power amplifier and a substrate coupled to the power amplifier. The substrate includes an encapsulation layer, a capacitor device located in the encapsulation layer, an inductor located in the encapsulation layer, at least one first dielectric layer coupled to a first surface of the encapsulation layer, and a plurality of first interconnects coupled to the first surface of the encapsulation layer. The plurality of first interconnects is located at least in the at least one first dielectric layer. The plurality of first interconnects is coupled to the capacitor device and the inductor. The inductor and the capacitor device are configured to be electrically coupled together to operate as elements of a matching network for the power amplifier. The capacitor device is configured to be coupled to ground.

A package that includes a power amplifier and a substrate coupled to the power amplifier. The substrate includes an encapsulation layer, a capacitor device located in the encapsulation layer, an inductor located in the encapsulation layer, at least one first dielectric layer coupled to a first surface of the encapsulation layer, and a plurality of first interconnects coupled to the first surface of the encapsulation layer. The plurality of first interconnects is located at least in the at least one first dielectric layer. The plurality of first interconnects is coupled to the capacitor device and the inductor. The inductor and the capacitor device are configured to be electrically coupled together to operate as elements of a matching network for the power amplifier. The capacitor device is configured to be coupled to ground.

Disclosed in the present invention are a radio frequency power amplifier based on current detection feedback and a chip. The radio frequency power amplifier comprises multiple stages of amplifier circuits and at least one current detection feedback circuit; the input end of the current detection feedback circuit is connected to the input end of a current stage of amplifier circuit among the multiple stages of amplifier circuits by means of a corresponding resistor, and the output end of the current detection feedback circuit is connected to the input end of at least one stage of amplifier circuit prior to the current stage of amplifier circuit. The current detection feedback circuit generates, according to the detected quiescent operating current of the current stage of amplifier circuit, a control voltage varying inversely with the quiescent operating current, so that the current detection feedback circuit outputs current varying positively with the control voltage.

Disclosed in the present invention are a radio frequency power amplifier based on current detection feedback and a chip. The radio frequency power amplifier comprises multiple stages of amplifier circuits and at least one current detection feedback circuit; the input end of the current detection feedback circuit is connected to the input end of a current stage of amplifier circuit among the multiple stages of amplifier circuits by means of a corresponding resistor, and the output end of the current detection feedback circuit is connected to the input end of at least one stage of amplifier circuit prior to the current stage of amplifier circuit. The current detection feedback circuit generates, according to the detected quiescent operating current of the current stage of amplifier circuit, a control voltage varying inversely with the quiescent operating current, so that the current detection feedback circuit outputs current varying positively with the control voltage.

A power control circuit includes: a voltage-current converter and a programmable current amplifier; the voltage-current converter is configured to detect an inputted output power control signal, and to convert the output power control signal to a control current and output same; and the programmable current amplifier is configured to receive the control current and output the amplified control current as a bias current of the power amplifier connected to the power control circuit.

A multiple-stage amplifier includes a driver stage die and a final stage die. The driver stage die includes a first type of semiconductor substrate (e.g., a silicon substrate), a first transistor, and an integrated portion of an interstage impedance matching circuit. A control terminal of the first transistor is electrically coupled to an RF signal input terminal of the driver stage die, and the integrated portion of the interstage impedance matching circuit is electrically coupled between a current-carrying terminal of the first transistor and an RF signal output terminal of the driver stage die. The second die includes a III-V semiconductor substrate (e.g., a GaN substrate) and a second transistor. A connection, which is a non-integrated portion of the interstage impedance matching circuit, is electrically coupled between the RF signal output terminal of the driver stage die and an RF signal input terminal of the final stage die.

A multiple-stage amplifier includes a driver stage die and a final stage die. The driver stage die includes a first type of semiconductor substrate (e.g., a silicon substrate), a first transistor, and an integrated portion of an interstage impedance matching circuit. A control terminal of the first transistor is electrically coupled to an RF signal input terminal of the driver stage die, and the integrated portion of the interstage impedance matching circuit is electrically coupled between a current-carrying terminal of the first transistor and an RF signal output terminal of the driver stage die. The second die includes a III-V semiconductor substrate (e.g., a GaN substrate) and a second transistor. A connection, which is a non-integrated portion of the interstage impedance matching circuit, is electrically coupled between the RF signal output terminal of the driver stage die and an RF signal input terminal of the final stage die.

A power amplifier circuitry (100) comprises: a transistor stack (110) comprising at least two stacked transistor units (112A, 112B, 112C) for amplifying input signals; wherein each stacked transistor unit (112A, 112B, 112C) comprises a plurality of controllable segments (120-1 to 120-N, 130-1 to 130-N, 140-1 to 140-N), each comprising a segment transistor (122, 132, 142), wherein source terminals (123, 133, 143) within each transistor unit are connected, drain terminals (125, 135, 145) within each transistor unit are connected and gate terminals (124, 134, 144) within each transistor unit are connected, wherein each segment transistor (122, 132, 142) further comprises a back gate terminal (126, 136, 146) for setting a body bias, wherein at least two of the segment transistors (122, 132, 142) within each transistor unit have independently connected back gate terminals (126, 136, 146); and a control unit (190) configured to control the body bias for selecting an amplifier class of each of the controllable segments (120-1 to 120-N, 130-1 to 130-N, 140-1 to 140-N) of each of the stacked transistor units (112A, 112B, 112C).

A power amplifier circuitry (100) comprises: a transistor stack (110) comprising at least two stacked transistor units (112A, 112B, 112C) for amplifying input signals; wherein each stacked transistor unit (112A, 112B, 112C) comprises a plurality of controllable segments (120-1 to 120-N, 130-1 to 130-N, 140-1 to 140-N), each comprising a segment transistor (122, 132, 142), wherein source terminals (123, 133, 143) within each transistor unit are connected, drain terminals (125, 135, 145) within each transistor unit are connected and gate terminals (124, 134, 144) within each transistor unit are connected, wherein each segment transistor (122, 132, 142) further comprises a back gate terminal (126, 136, 146) for setting a body bias, wherein at least two of the segment transistors (122, 132, 142) within each transistor unit have independently connected back gate terminals (126, 136, 146); and a control unit (190) configured to control the body bias for selecting an amplifier class of each of the controllable segments (120-1 to 120-N, 130-1 to 130-N, 140-1 to 140-N) of each of the stacked transistor units (112A, 112B, 112C).

An amplifier includes a Field Effect Transistor (FET) or a Bipolar Junction Transistor (BJT) with “hard saturation.”; where the FET or the BJT to has a nearly constant drain or collector current when the drain or collector voltage is greater than the pinchoff voltage. The amplifier further includes a bias network, configured to provide a DC voltage to the FET or the BJT, a means for isolating the DC voltage from the matching network, an electrical load, and a matching network which transforms the electrical load to a resistance between the drain and the source or the collector and emitter which causes the drain or collector voltage to be greater than the pinchoff voltage over the entire cycle of the sinusoidal voltage applied to the gate, whereby the amplifier is linear.