A method for converting voltage is disclosed, including implementing a first DC-DC converter in a power management unit; implementing a second DC-DC converter in the power management unit; implementing a controller communicatively coupled to a first output line of the first DC-DC converter and communicatively coupled to a second output line of the second DC-DC converter; coupling the power management unit to a supply voltage; and providing one or more output voltages on the first output line and the second output line.

Disclosed is a bias circuit for a radio frequency power amplifier, including a resistor voltage divider network, a power amplifier coupled with the resistor voltage divider network and a bias voltage adjusting loop coupled to the resistor voltage divider network and including one voltage divider resistor and one transistor pair; one terminal of the voltage divider resistor is connected with a reference voltage, and an other terminal is coupled with a gate of the first metal oxide semiconductor transistor; the transistor pair includes a first metal oxide semiconductor transistor and a second metal oxide semiconductor transistor, where a gate of the second metal oxide semiconductor transistor is coupled to the gate of the first metal oxide semiconductor transistor.

Disclosed is a bias circuit for a radio frequency power amplifier, including a resistor voltage divider network, a power amplifier coupled with the resistor voltage divider network and a bias voltage adjusting loop coupled to the resistor voltage divider network and including one voltage divider resistor and one transistor pair; one terminal of the voltage divider resistor is connected with a reference voltage, and an other terminal is coupled with a gate of the first metal oxide semiconductor transistor; the transistor pair includes a first metal oxide semiconductor transistor and a second metal oxide semiconductor transistor, where a gate of the second metal oxide semiconductor transistor is coupled to the gate of the first metal oxide semiconductor transistor.

An electronic circuit includes a differential output circuit that produces a differential output signal at a differential output. A primary winding of a balun has a first balun terminal coupled to a first differential output terminal, and a second balun terminal coupled to a second differential output terminal. A configurable harmonic reduction circuit includes first and second configurable shunt capacitance circuits coupled between the first differential output terminal or the second differential output terminal, respectively, and a ground reference node. A control circuit receives tuning data associated with a calibrated tuning state. The tuning data indicates a first and second calibrated capacitance values, which are unequal, for the first and second configurable shunt capacitance circuits, respectively. The control circuit controls the first configurable shunt capacitance circuit to have the first calibrated capacitance value, and controls the second configurable shunt capacitance circuit to have the second calibrated capacitance value.

Example embodiments relate to Doherty amplifiers. One Doherty amplifier includes a packaged main amplifier that includes a main input lead for receiving a main RF signal, a main power transistor for amplifying the main RF signal, and a main output lead for outputting the main RF signal amplified by the main power transistor. The Doherty amplifier also includes a packaged peak amplifier that includes a peak input lead assembly for receiving a peak RF a first peak power transistor configured for amplifying a part of the peak RF signal, a second peak power transistor configured for amplifying a remaining part of the peak RF signal, and a peak output lead for combining the part of the peak RF signal amplified by the first peak power transistor and the remaining part of the peak RF signal amplified by the second peak power transistor into an amplified peak RF signal.

Example embodiments relate to radiofrequency, RF, amplifiers and electronic devices that include RF amplifiers. One example RF amplifier includes a splitter configured to split an RF input signal received at an input of the RF amplifier into a plurality of RF signal parts. The RF amplifier also includes a plurality of Doherty amplifiers, each Doherty amplifier having a main amplifier and a peak amplifier. Each Doherty amplifier is configured to amplify a respective RF signal part and output a respective amplified RF signal part. Additionally, the RF amplifier includes a combiner. The combiner is configured to combine the amplified RF signal parts from the plurality of Doherty amplifiers into an RF output signal and output the RE output signal. The combiner includes a plurality of inputs and an output. Each input of the combiner is connected to an output of a respective Doherty amplifier among the plurality of Doherty amplifiers.

Solder bumps are placed in direct contact with the silicon substrate of an amplifier integrated circuit having a flip chip configuration. A plurality of amplifier transistor arrays generate waste heat that promotes thermal run away of the amplifier if not directed out of the integrated circuit. The waste heat flows through the thermally conductive silicon substrate and out the solder bump to a heat-sinking plane of an interposer connected to the amplifier integrated circuit via the solder bumps.

Solder bumps are placed in direct contact with the silicon substrate of an amplifier integrated circuit having a flip chip configuration. A plurality of amplifier transistor arrays generate waste heat that promotes thermal run away of the amplifier if not directed out of the integrated circuit. The waste heat flows through the thermally conductive silicon substrate and out the solder bump to a heat-sinking plane of an interposer connected to the amplifier integrated circuit via the solder bumps.

A semiconductor device has a semiconductor substrate, and multiple first bipolar transistors on the first primary surface side of the semiconductor substrate. The first bipolar transistors have a first height between an emitter layer and an emitter electrode in the direction perpendicular to the first primary surface. The semiconductor device further has at least one second bipolar transistor on the first primary surface side of the semiconductor substrate. The second bipolar transistor have a second height, greater than the first height, between an emitter layer and an emitter electrode in the direction perpendicular to the first primary surface. Also, the semiconductor has a first bump stretching over the multiple first bipolar transistors and the at least one second bipolar transistor.

A device includes a package body including a central flange and an amplifier module mounted to the central flange of the surface-mount device. The amplifier module includes a module substrate mounted to the central flange. The module substrate includes a first die mount window, a first circuitry on a first surface of the module substrate, a second circuitry on the first surface of the module substrate, and a first amplifier die mounted on the central flange. The first amplifier die is at least partially disposed within the first die mount window and the first amplifier die is electrically connected to the first circuitry and the second circuitry. The first circuitry is electrically connected to a first lead of the package body and the second circuitry is electrically connected to a second lead of the package body.