A semiconductor-on-insulator die can include a power amplifier configured to amplify a radio frequency input signal having a fundamental frequency. The die can further include an output matching circuit including first and second second-order harmonic rejection circuits configured to resonate at about two times the fundamental frequency and a third order harmonic rejection circuit configured to resonate at about three times the fundamental frequency.

A semiconductor-on-insulator die can include a power amplifier configured to amplify a radio frequency input signal having a fundamental frequency. The die can further include an output matching circuit including first and second second-order harmonic rejection circuits configured to resonate at about two times the fundamental frequency and a third order harmonic rejection circuit configured to resonate at about three times the fundamental frequency.

The present disclosure provides a power amplifier and an electrical device. The two-stage power amplifier architecture is tuned staggered before power combining. A previous stage matching network and its input matching are split into a cascaded staggered tuning, such that the center frequency is at frequency point 1 less than the design frequency point and frequency point 2 greater than design frequency point, and then the power combining stage is tuned at the design frequency point. At advanced process nodes (such as 65 nm or below), compared with the known architecture, in-band signal quality and out-of-band filtering effect of the power amplifier chip integrating this architecture will be better when using the same number of transformers (same area), the reliability will be better. Due to its good flatness within the band, this architecture is especially suitable for carrier aggregation communication occasions.

The present disclosure provides a power amplifier and an electrical device. The two-stage power amplifier architecture is tuned staggered before power combining. A previous stage matching network and its input matching are split into a cascaded staggered tuning, such that the center frequency is at frequency point 1 less than the design frequency point and frequency point 2 greater than design frequency point, and then the power combining stage is tuned at the design frequency point. At advanced process nodes (such as 65 nm or below), compared with the known architecture, in-band signal quality and out-of-band filtering effect of the power amplifier chip integrating this architecture will be better when using the same number of transformers (same area), the reliability will be better. Due to its good flatness within the band, this architecture is especially suitable for carrier aggregation communication occasions.

A power amplifier circuit includes a first transistor disposed on a semiconductor substrate; a second transistor that supplies a bias current based on a first current which is a part of a control current to the first transistor; a current output element in which a current flowing therethrough increases in accordance with a rise in temperature; and a wiring portion including a plurality of metal layers that are electrically connected to an emitter of the first transistor and that are stacked one on top of another so as to oppose the semiconductor substrate. At least one metal layer among the plurality of metal layers extends so as to overlap an area extending from at least a part of a first disposition area in which the first transistor is disposed to a second disposition area in which the current output element is disposed in plan view of the semiconductor substrate.

A power amplifier circuit includes a first transistor disposed on a semiconductor substrate; a second transistor that supplies a bias current based on a first current which is a part of a control current to the first transistor; a current output element in which a current flowing therethrough increases in accordance with a rise in temperature; and a wiring portion including a plurality of metal layers that are electrically connected to an emitter of the first transistor and that are stacked one on top of another so as to oppose the semiconductor substrate. At least one metal layer among the plurality of metal layers extends so as to overlap an area extending from at least a part of a first disposition area in which the first transistor is disposed to a second disposition area in which the current output element is disposed in plan view of the semiconductor substrate.

Disclosed in the present invention are a balanced radio frequency power amplifier, a chip and a communication terminal. The radio frequency power amplifier divides, by means of a 90-degree power splitter unit, a radio frequency input signal into two equal-amplitude signals having a phase difference of 90 degrees, the two radio frequency input signals are amplified and then inputted into an adjustable 90 -degree power combiner, and the values of a adjustable capacitor and an adjustable resistor in the adjustable 90-degree power combiner are controlled by means of a control unit, so as to synthesize the two radio frequency input signals into one radio frequency input signal when the phase difference and amplitude difference of the two signals at different frequencies are the smallest, and to input the radio frequency input signal into a circuit of the next stage by means of a specific radio frequency transmission path.

Disclosed in the present invention are a balanced radio frequency power amplifier, a chip and a communication terminal. The radio frequency power amplifier divides, by means of a 90-degree power splitter unit, a radio frequency input signal into two equal-amplitude signals having a phase difference of 90 degrees, the two radio frequency input signals are amplified and then inputted into an adjustable 90 -degree power combiner, and the values of a adjustable capacitor and an adjustable resistor in the adjustable 90-degree power combiner are controlled by means of a control unit, so as to synthesize the two radio frequency input signals into one radio frequency input signal when the phase difference and amplitude difference of the two signals at different frequencies are the smallest, and to input the radio frequency input signal into a circuit of the next stage by means of a specific radio frequency transmission path.

A power amplifier, for a transmitter circuit is disclosed, which comprises at least one field-effect transistor having a gate terminal and a bulk terminal. The at least one field-effect transistor is configured to receive an input voltage at the gate terminal and a dynamic bias voltage at the bulk terminal. The power amplifier comprises a bias-voltage generation circuit configured to generate the dynamic bias voltage as a nonlinear function of an envelope of input signal. The input voltage is a linear function of the input signal. The bias-voltage generation circuit comprises a rectifier circuit configured to generate a rectified input voltage and an amplifier circuit, operatively connected to the rectifier circuit, configured to generate the dynamic bias voltage based on the rectified input voltage. The amplifier circuit is a variable-gain amplifier circuit and the power amplifier comprises a control circuit configured to tune the gain of the amplifier circuit.

A power amplifier, for a transmitter circuit is disclosed, which comprises at least one field-effect transistor having a gate terminal and a bulk terminal. The at least one field-effect transistor is configured to receive an input voltage at the gate terminal and a dynamic bias voltage at the bulk terminal. The power amplifier comprises a bias-voltage generation circuit configured to generate the dynamic bias voltage as a nonlinear function of an envelope of input signal. The input voltage is a linear function of the input signal. The bias-voltage generation circuit comprises a rectifier circuit configured to generate a rectified input voltage and an amplifier circuit, operatively connected to the rectifier circuit, configured to generate the dynamic bias voltage based on the rectified input voltage. The amplifier circuit is a variable-gain amplifier circuit and the power amplifier comprises a control circuit configured to tune the gain of the amplifier circuit.